1 /* $NetBSD: cpu.h,v 1.18 1995/03/23 20:19:21 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 */ 40 41 /* 42 * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved. 43 * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot 44 45 * Redistribution of this source code or any part thereof is permitted, 46 * provided that the following conditions are met: 47 * 1) Utilized source contains the copyright message above, this list 48 * of conditions, and the following disclaimer. 49 * 2) Binary objects containing compiled source reproduce the 50 * copyright notice above on startup. 51 * 52 * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any 53 * warranties of ANY kind are disclaimed. We don't even claim that it 54 * won't crash your hard disk. Basically, we want a little credit if 55 * it works, but we don't want to get mail-bombed if it doesn't. 56 */ 57 58 /* 59 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 60 * 61 * @(#)cpu.h 7.7 (Berkeley) 6/27/91 62 */ 63 64 /* 65 ALICE 66 BG -- Sat May 23 23:58:23 EDT 1992 67 Exported defines and stuff unique to mac68k. 68 A lot of this stuff is really specific to the m68k, not just the macs, 69 but there isn't time to do anything about that right now... 70 */ 71 72 #ifndef _MACHINE_CPU_H_ 73 #define _MACHINE_CPU_H_ 1 74 75 /* 76 * definitions of cpu-dependent requirements 77 * referenced in generic code 78 */ 79 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 80 81 #define cpu_swapin(p) /* nothing */ 82 #define cpu_exec(p) /* nothing */ 83 #define cpu_wait(p) /* nothing */ 84 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 85 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 86 87 /* 88 * Arguments to hardclock, softclock and gatherstats 89 * encapsulate the previous machine state in an opaque 90 * clockframe; for hp300, use just what the hardware 91 * leaves on the stack. 92 */ 93 94 struct clockframe { 95 u_short sr; 96 u_long pc; 97 u_short vo; 98 }; 99 100 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 101 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 102 #define CLKF_PC(framep) ((framep)->pc) 103 #define CLKF_INTR(framep) (0) /* XXX should use PSL_M (see hp300) */ 104 105 /* 106 * Preempt the current process if in interrupt from user mode, 107 * or after the current trap/syscall if in system mode. 108 */ 109 #define need_resched() { want_resched++; aston(); } 110 111 /* 112 * Give a profiling tick to the current process from the softclock 113 * interrupt. Request an ast to send us through trap(), 114 * marking the proc as needing a profiling tick. 115 */ 116 #define profile_tick(p, framep) ( (p)->p_flag |= P_OWEUPC, aston() ) 117 #define need_proftick(p) ( (p)->p_flag |= P_OWEUPC, aston() ) 118 119 /* 120 * Notify the current process (p) that it has a signal pending, 121 * process as soon as possible. 122 */ 123 #define signotify(p) aston() 124 125 #define aston() (astpending++) 126 127 int astpending; /* need to trap before returning to user mode */ 128 int want_resched; /* resched() was called */ 129 130 /* 131 * simulated software interrupt register 132 */ 133 extern unsigned char ssir; 134 135 #define SIR_NET 0x1 136 #define SIR_CLOCK 0x2 137 #define SIR_SERIAL 0x4 138 139 #define siroff(x) ssir &= ~(x) 140 #define setsoftnet() ssir |= SIR_NET 141 #define setsoftclock() ssir |= SIR_CLOCK 142 #define setsoftserial() ssir |= SIR_SERIAL 143 144 #define CPU_CONSDEV 1 145 #define CPU_MAXID 2 146 147 #define CTL_MACHDEP_NAMES { \ 148 { 0, 0 }, \ 149 { "console_device", CTLTYPE_STRUCT }, \ 150 } 151 152 /* values for machineid -- 153 * These are equivalent to the MacOS Gestalt values. */ 154 #define MACH_MACII 6 155 #define MACH_MACIIX 7 156 #define MACH_MACIICX 8 157 #define MACH_MACSE30 9 158 #define MACH_MACIICI 11 159 #define MACH_MACIIFX 13 160 #define MACH_MACIISI 18 161 #define MACH_MACQ900 20 162 #define MACH_MACPB170 21 163 #define MACH_MACQ700 22 164 #define MACH_MACCLASSICII 23 165 #define MACH_MACPB100 24 166 #define MACH_MACPB140 25 167 #define MACH_MACQ950 26 168 #define MACH_MACLCIII 27 169 #define MACH_MACPB210 29 170 #define MACH_MACC650 30 171 #define MACH_MACPB230 32 172 #define MACH_MACPB180 33 173 #define MACH_MACPB160 34 174 #define MACH_MACQ800 35 175 #define MACH_MACQ650 36 176 #define MACH_MACLCII 37 177 #define MACH_MACPB250 38 178 #define MACH_MACIIVI 44 179 #define MACH_MACP600 45 180 #define MACH_MACIIVX 48 181 #define MACH_MACCCLASSIC 49 182 #define MACH_MACPB165C 50 183 #define MACH_MACC610 52 184 #define MACH_MACQ610 53 185 #define MACH_MACPB145 54 186 #define MACH_MACLC520 56 187 #define MACH_MACC660AV 60 188 #define MACH_MACP460 62 189 #define MACH_MACPB180C 71 190 #define MACH_MACPB270 77 191 #define MACH_MACQ840AV 78 192 #define MACH_MACP550 80 193 #define MACH_MACPB165 84 194 #define MACH_MACTV 88 195 #define MACH_MACLC475 89 196 #define MACH_MACLC575 92 197 #define MACH_MACQ605 94 198 199 /* 200 * Machine classes. These define subsets of the above machines. 201 */ 202 #define MACH_CLASSH 0x0000 /* Hopeless cases... */ 203 #define MACH_CLASSII 0x0001 /* MacII class */ 204 #define MACH_CLASSIIci 0x0002 /* Have RBV, but no Egret */ 205 #define MACH_CLASSIIsi 0x0003 /* Similar to IIci -- Have Egret. */ 206 #define MACH_CLASSIIfx 0x0004 /* The IIfx is in a class by itself. */ 207 #define MACH_CLASSPB 0x0008 /* Powerbooks. Power management. */ 208 #define MACH_CLASSLC 0x0010 /* Low-Cost/Performa/Wal-Mart Macs. */ 209 #define MACH_CLASSQ 0x0100 /* Centris/Quadras. */ 210 211 /* MF processor passed in */ 212 #define MACH_68020 0 213 #define MACH_68030 1 214 #define MACH_68040 2 215 #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */ 216 217 /* Defines for mmutype */ 218 #define MMU_68040 -2 219 #define MMU_68030 -1 220 /* #define MMU_HP 0 Just a reminder as to where this came from. */ 221 #define MMU_68851 1 222 223 /* values for cpuspeed (not really related to clock speed due to caches) */ 224 #define MHZ_8 1 225 #define MHZ_16 2 226 #define MHZ_25 3 227 #define MHZ_33 4 228 #define MHZ_40 5 229 230 #ifdef _KERNEL 231 struct mac68k_machine_S { 232 int cpu_model_index; 233 /* 234 * Misc. info from booter. 235 */ 236 int machineid; 237 int mach_processor; 238 int mach_memsize; 239 int booter_version; 240 /* 241 * Debugging flags. 242 */ 243 int do_graybars; 244 int serial_boot_echo; 245 int serial_console; 246 /* 247 * Misc. hardware info. 248 */ 249 int scsi80; /* Has NCR 5380 */ 250 int scsi96; /* Has NCR 53C96 */ 251 int scsi96_2; /* Has 2nd 53C96 */ 252 int sonic; /* Has SONIC e-net */ 253 254 int sccClkConst; /* "Constant" for SCC bps */ 255 }; 256 257 /* What kind of model is this */ 258 struct cpu_model_info { 259 int machineid; /* MacOS Gestalt value. */ 260 char *model_major; /* Make this distinction to save a few */ 261 char *model_minor; /* bytes--might be useful, too. */ 262 int class; /* Rough class of machine. */ 263 /* forwarded romvec_s is defined in mac68k/macrom.h */ 264 struct romvec_s *rom_vectors; /* Pointer to our known rom vectors */ 265 }; 266 extern struct cpu_model_info *current_mac_model; 267 268 extern unsigned long IOBase; /* Base address of I/O */ 269 extern unsigned long NuBusBase; /* Base address of NuBus */ 270 271 extern struct mac68k_machine_S mac68k_machine; 272 extern int mmutype, cpu040; 273 extern unsigned long load_addr ; 274 #endif /* _KERNEL */ 275 276 /* physical memory sections */ 277 #define ROMBASE (0x40800000) 278 #define ROMTOP (0x41800000) /* 16MB should be plenty! */ 279 #define ROMMAPSIZE btoc(ROMTOP - ROMBASE) /* 16k of page tables. */ 280 281 /* This should not be used. Use IOBase, instead. */ 282 #define INTIOBASE (0x50000000) 283 284 #define INTIOTOP (IOBase+0x01000000) 285 #define IIOMAPSIZE btoc(0x01000000) 286 287 /* XXX -- Need to do something about superspace. */ 288 #ifdef NO_SUPER_SPACE_YET 289 #define NBSBASE 0x60000000 /* NUBUS Super space */ 290 #define NBSTOP 0xF0000000 291 #endif 292 #define NBBASE 0xF9000000 /* NUBUS space */ 293 #define NBTOP 0xFF000000 /* NUBUS space */ 294 #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */ 295 #define NBMEMSIZE 0x01000000 /* 16 megs per card */ 296 #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */ 297 298 /* 299 * 68851 and 68030 MMU 300 */ 301 #define PMMU_LVLMASK 0x0007 302 #define PMMU_INV 0x0400 303 #define PMMU_WP 0x0800 304 #define PMMU_ALV 0x1000 305 #define PMMU_SO 0x2000 306 #define PMMU_LV 0x4000 307 #define PMMU_BE 0x8000 308 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 309 310 /* 680X0 function codes */ 311 #define FC_USERD 1 /* user data space */ 312 #define FC_USERP 2 /* user program space */ 313 #define FC_SUPERD 5 /* supervisor data space */ 314 #define FC_SUPERP 6 /* supervisor program space */ 315 #define FC_CPU 7 /* CPU space */ 316 317 /* fields in the 68020 cache control register */ 318 #define IC_ENABLE 0x0001 /* enable instruction cache */ 319 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 320 #define IC_CE 0x0004 /* clear instruction cache entry */ 321 #define IC_CLR 0x0008 /* clear entire instruction cache */ 322 323 /* additional fields in the 68030 cache control register */ 324 #define IC_BE 0x0010 /* instruction burst enable */ 325 #define DC_ENABLE 0x0100 /* data cache enable */ 326 #define DC_FREEZE 0x0200 /* data cache freeze */ 327 #define DC_CE 0x0400 /* clear data cache entry */ 328 #define DC_CLR 0x0800 /* clear entire data cache */ 329 #define DC_BE 0x1000 /* data burst enable */ 330 #define DC_WA 0x2000 /* write allocate */ 331 332 /* fields in the 68040 cache control register */ 333 #define IC40_ENABLE 0x00008000 /* enable instruction cache */ 334 #define DC40_ENABLE 0x80000000 /* enable data cache */ 335 336 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 337 #define CACHE_OFF (DC_CLR|IC_CLR) 338 #define CACHE_CLR (CACHE_ON) 339 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 340 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 341 342 /* 68040 cache control */ 343 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 344 #define CACHE40_OFF 0x00000000 345 346 #endif /* !_MACHINE_CPU_H_ */ 347