1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved. 41 * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot 42 43 * Redistribution of this source code or any part thereof is permitted, 44 * provided that the following conditions are met: 45 * 1) Utilized source contains the copyright message above, this list 46 * of conditions, and the following disclaimer. 47 * 2) Binary objects containing compiled source reproduce the 48 * copyright notice above on startup. 49 * 50 * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any 51 * warranties of ANY kind are disclaimed. We don't even claim that it 52 * won't crash your hard disk. Basically, we want a little credit if 53 * it works, but we don't want to get mail-bombed if it doesn't. 54 */ 55 56 /* 57 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 58 * 59 * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91 60 * $Id: cpu.h,v 1.10 1994/05/06 17:39:19 briggs Exp $ 61 */ 62 63 /* 64 ALICE 65 BG -- Sat May 23 23:58:23 EDT 1992 66 Exported defines and stuff unique to mac68k. 67 A lot of this stuff is really specific to the m68k, not just the macs, 68 but there isn't time to do anything about that right now... 69 */ 70 71 #ifndef _MACHINE_CPU_H_ 72 #define _MACHINE_CPU_H_ 1 73 74 /* 75 * definitions of cpu-dependent requirements 76 * referenced in generic code 77 */ 78 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 79 80 /* 81 * function vs. inline configuration; 82 * these are defined to get generic functions 83 * rather than inline or machine-dependent implementations 84 */ 85 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 86 #undef NEED_FFS /* don't need ffs function */ 87 #undef NEED_BCMP /* don't need bcmp function */ 88 #undef NEED_STRLEN /* don't need strlen function */ 89 90 #define cpu_exec(p) /* nothing */ 91 #define cpu_wait(p) /* nothing */ 92 93 /* 94 * Arguments to hardclock, softclock and gatherstats 95 * encapsulate the previous machine state in an opaque 96 * clockframe; for hp300, use just what the hardware 97 * leaves on the stack. 98 */ 99 100 struct clockframe { 101 int ps; 102 int pc; 103 }; 104 105 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 106 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 107 #define CLKF_PC(framep) ((framep)->pc) 108 #define CLKF_INTR(framep) (0) /* XXX should have an interrupt stack? */ 109 110 /* 111 * Preempt the current process if in interrupt from user mode, 112 * or after the current trap/syscall if in system mode. 113 */ 114 #define need_resched() { want_resched++; aston(); } 115 116 /* 117 * Give a profiling tick to the current process from the softclock 118 * interrupt. Request an ast to send us through trap(), 119 * marking the proc as needing a profiling tick. 120 */ 121 #define profile_tick(p, framep) ( (p)->p_flag |= P_OWEUPC, aston() ) 122 #define need_proftick(p) ( (p)->p_flag |= P_OWEUPC, aston() ) 123 124 /* 125 * Notify the current process (p) that it has a signal pending, 126 * process as soon as possible. 127 */ 128 #define signotify(p) aston() 129 130 #define aston() (astpending++) 131 132 int astpending; /* need to trap before returning to user mode */ 133 int want_resched; /* resched() was called */ 134 135 /* 136 * simulated software interrupt register 137 */ 138 extern unsigned char ssir; 139 140 #define SIR_NET 0x1 141 #define SIR_CLOCK 0x2 142 #define SIR_SERIAL 0x4 143 144 #define siroff(x) ssir &= ~(x) 145 #define setsoftnet() ssir |= SIR_NET 146 #define setsoftclock() ssir |= SIR_CLOCK 147 #define setsoftserial() ssir |= SIR_SERIAL 148 149 150 /* values for machineid -- 151 * These are equivalent to the MacOS Gestalt values. */ 152 #define MACH_MACII 6 153 #define MACH_MACIIX 7 154 #define MACH_MACIICX 8 155 #define MACH_MACSE30 9 156 #define MACH_MACIICI 11 157 #define MACH_MACIIFX 13 158 #define MACH_MACIISI 18 159 #define MACH_MACQ900 20 160 #define MACH_MACPB170 21 161 #define MACH_MACQ700 22 162 #define MACH_MACCLASSICII 23 163 #define MACH_MACPB100 24 164 #define MACH_MACPB140 25 165 #define MACH_MACQ950 26 166 #define MACH_MACLCIII 27 167 #define MACH_MACPB210 29 168 #define MACH_MACC650 30 169 #define MACH_MACPB230 32 170 #define MACH_MACPB180 33 171 #define MACH_MACPB160 34 172 #define MACH_MACQ800 35 173 #define MACH_MACQ650 36 174 #define MACH_MACLCII 37 175 #define MACH_MACPB250 38 176 #define MACH_MACIIVI 44 177 #define MACH_MACP600 45 178 #define MACH_MACIIVX 48 179 #define MACH_MACCCLASSIC 49 180 #define MACH_MACPB165C 50 181 #define MACH_MACC610 52 182 #define MACH_MACQ610 53 183 #define MACH_MACPB145 54 184 #define MACH_MACLC520 56 185 #define MACH_MACC660AV 60 186 #define MACH_MACP460 62 187 #define MACH_MACPB180C 71 188 #define MACH_MACPB270 77 189 #define MACH_MACQ840AV 78 190 #define MACH_MACP550 80 191 #define MACH_MACPB165 84 192 #define MACH_MACTV 88 193 #define MACH_MACLC475 89 194 #define MACH_MACLC575 92 195 #define MACH_MACQ605 94 196 197 /* MF processor passed in */ 198 #define MACH_68020 0 199 #define MACH_68030 1 200 #define MACH_68040 2 201 #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */ 202 203 /* Defines for mmutype */ 204 #define MMU_68851 -1 205 #define MMU_68030 0 206 #define MMU_68040 1 207 208 /* values for cpuspeed (not really related to clock speed due to caches) */ 209 #define MHZ_8 1 210 #define MHZ_16 2 211 #define MHZ_25 3 212 #define MHZ_33 4 213 #define MHZ_40 5 214 215 #ifdef KERNEL 216 extern int machineid, ectype; 217 extern char *intiobase, *intiolimit; 218 extern char *extiobase, *extiolimit; 219 220 extern int mach_processor, mach_memsize; 221 extern int do_graybars, serial_boot_echo; 222 extern int booter_version; 223 extern int mmutype, cpu040; 224 #endif 225 226 /* physical memory sections */ 227 #define ROMBASE (0x40000000) 228 #define INTIOBASE (0x50000000) 229 #define INTIOTOP (0x51000000) /* ~ 128 K */ 230 #define IIOMAPSIZE btoc(INTIOTOP - INTIOBASE) 231 232 /* ALICE 05/23/92 BG -- These need to be changed. */ 233 #ifdef NO_SUPER_SPACE_YET 234 #define NBSBASE 0x60000000 /* NUBUS Super space */ 235 #define NBSTOP 0xF0000000 236 #endif 237 #define NBBASE 0xF9000000 /* NUBUS space */ 238 #define NBTOP 0xFF000000 /* NUBUS space */ 239 #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */ 240 #define NBMEMSIZE 0x01000000 /* 16 megs per card */ 241 #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */ 242 243 /* 244 * IO space: 245 * 246 * Internal IO space is mapped in the kernel from ``intiobase'' to 247 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 248 * conversion between physical and kernel virtual addresses is easy. 249 */ 250 #define ISIIOVA(va) \ 251 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 252 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 253 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 254 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 255 256 /* 257 ALICE 05/24/92,13:25:19 BG -- We need to make sure to map NuBus memory in 258 the kernel, too. 259 ALICE 06/29/92,20:40:00 LK -- I did that, thank you very much. Been there. 260 */ 261 262 263 /* 264 * 68851 and 68030 MMU 265 */ 266 #define PMMU_LVLMASK 0x0007 267 #define PMMU_INV 0x0400 268 #define PMMU_WP 0x0800 269 #define PMMU_ALV 0x1000 270 #define PMMU_SO 0x2000 271 #define PMMU_LV 0x4000 272 #define PMMU_BE 0x8000 273 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 274 275 /* 680X0 function codes */ 276 #define FC_USERD 1 /* user data space */ 277 #define FC_USERP 2 /* user program space */ 278 #define FC_SUPERD 5 /* supervisor data space */ 279 #define FC_SUPERP 6 /* supervisor program space */ 280 #define FC_CPU 7 /* CPU space */ 281 282 /* fields in the 68020 cache control register */ 283 #define IC_ENABLE 0x0001 /* enable instruction cache */ 284 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 285 #define IC_CE 0x0004 /* clear instruction cache entry */ 286 #define IC_CLR 0x0008 /* clear entire instruction cache */ 287 288 /* additional fields in the 68030 cache control register */ 289 #define IC_BE 0x0010 /* instruction burst enable */ 290 #define DC_ENABLE 0x0100 /* data cache enable */ 291 #define DC_FREEZE 0x0200 /* data cache freeze */ 292 #define DC_CE 0x0400 /* clear data cache entry */ 293 #define DC_CLR 0x0800 /* clear entire data cache */ 294 #define DC_BE 0x1000 /* data burst enable */ 295 #define DC_WA 0x2000 /* write allocate */ 296 297 /* fields in the 68040 cache control register */ 298 #define IC40_ENABLE 0x00008000 /* enable instruction cache */ 299 #define DC40_ENABLE 0x80000000 /* enable data cache */ 300 301 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 302 #define CACHE_OFF (DC_CLR|IC_CLR) 303 #define CACHE_CLR (CACHE_ON) 304 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 305 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 306 307 /* 68040 cache control */ 308 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 309 #define CACHE40_OFF 0x00000000 310 311 #endif /* !_MACHINE_CPU_H_ */ 312