1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 /*- 39 * Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo, 40 * Michael L. Finch, Bradley A. Grantham, and 41 * Lawrence A. Kesteloot 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by the Alice Group. 55 * 4. The names of the Alice Group or any of its members may not be used 56 * to endorse or promote products derived from this software without 57 * specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 68 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 */ 71 #ident "$Id: cpu.h,v 1.1.1.1 1993/09/29 06:09:24 briggs Exp $" 72 73 /* 74 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 75 * 76 * @(#)cpu.h 7.7 (Berkeley) 6/27/91 77 */ 78 79 /* 80 ALICE 81 BG -- Sat May 23 23:58:23 EDT 1992 82 Exported defines and stuff unique to macII/68k. 83 */ 84 85 /* 86 * definitions of cpu-dependent requirements 87 * referenced in generic code 88 */ 89 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 90 91 /* 92 * function vs. inline configuration; 93 * these are defined to get generic functions 94 * rather than inline or machine-dependent implementations 95 */ 96 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 97 #undef NEED_FFS /* don't need ffs function */ 98 #undef NEED_BCMP /* don't need bcmp function */ 99 #undef NEED_STRLEN /* don't need strlen function */ 100 101 /* ALICE BG -- Sun May 24 11:31:35 EDT 1992 -- what the hell do these things */ 102 /* do? */ 103 #define cpu_exec(p) /* nothing */ 104 #define cpu_wait(p) /* nothing */ 105 106 /* 107 * Arguments to hardclock, softclock and gatherstats 108 * encapsulate the previous machine state in an opaque 109 * clockframe; for hp300, use just what the hardware 110 * leaves on the stack. 111 */ 112 /* ALICE 05/23/92 BG -- Oh, no. What does a VIA intleave on the stack? */ 113 /* ALICE 06/27/92 LK -- Make sure hardware clock routine does this: */ 114 115 typedef struct intrframe { 116 int pc; 117 int ps; 118 } clockframe; 119 120 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 121 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 122 #define CLKF_PC(framep) ((framep)->pc) 123 124 /* 125 * Preempt the current process if in interrupt from user mode, 126 * or after the current trap/syscall if in system mode. 127 */ 128 #define need_resched() { want_resched++; aston(); } 129 130 /* 131 * Give a profiling tick to the current process from the softclock 132 * interrupt. Request an ast to send us through trap(), 133 * marking the proc as needing a profiling tick. 134 */ 135 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 136 137 /* 138 * Notify the current process (p) that it has a signal pending, 139 * process as soon as possible. 140 */ 141 #define signotify(p) aston() 142 143 #define aston() (astpending++) 144 145 int astpending; /* need to trap before returning to user mode */ 146 int want_resched; /* resched() was called */ 147 148 149 /* 150 * simulated software interrupt register 151 */ 152 extern unsigned char ssir; 153 154 #define SIR_NET 0x1 155 #define SIR_CLOCK 0x2 156 157 #define siroff(x) ssir &= ~(x) 158 #define setsoftnet() ssir |= SIR_NET 159 #define setsoftclock() ssir |= SIR_CLOCK 160 161 162 163 /* 164 * The rest of this should probably be moved to ../macII/macIIcpu.h, 165 * although some of it could probably be put into generic 68k headers. 166 */ 167 168 /* values for machineid */ 169 /* BARF MF - some values from the thinkc gesalt include file */ 170 #define MACH_MAC2 6 171 #define MACH_MAC2X 7 172 #define MACH_MAC2SI 18 173 #define MACH_MAC2CI 11 174 #define MACH_MAC2CX 8 175 #define MACH_MAC2FX 13 176 #define MACH_MACSE30 14 177 178 /* MF processor passed in */ 179 #define MACH_68020 0 180 #define MACH_68030 1 181 #define MACH_68040 2 182 #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */ 183 184 /* values for cpuspeed (not really related to clock speed due to caches) */ 185 #define MHZ_8 1 186 #define MHZ_16 2 187 #define MHZ_25 3 188 #define MHZ_33 4 189 #define MHZ_40 5 190 191 #ifdef KERNEL 192 extern int machineid, ectype; 193 extern char *intiobase, *intiolimit; 194 extern char *extiobase, *extiolimit; 195 196 #endif 197 198 /* physical memory sections */ 199 #define ROMBASE (0x40000000) 200 #define IOBASE (0x50000000) 201 #define IOTOP (0x51000000) /* ~ 128 K */ 202 #define IOMAPSIZE btoc(IOTOP - IOBASE) 203 204 /* ALICE 05/23/92 BG -- These need to be changed. */ 205 #ifdef NO_SUPER_SPACE_YET 206 #define NBSBASE 0x60000000 /* NUBUS Super space */ 207 #define NBSTOP 0xF0000000 208 #endif 209 #define NBBASE 0xF9000000 /* NUBUS space */ 210 #define NBTOP 0xFF000000 /* NUBUS space */ 211 #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */ 212 #define NBMEMSIZE 0x01000000 /* 16 megs per card */ 213 #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */ 214 215 /* 216 * IO space: 217 * 218 * Internal IO space is mapped in the kernel from ``intiobase'' to 219 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 220 * conversion between physical and kernel virtual addresses is easy. 221 */ 222 #ifdef WE_DONT_KNOW_WHAT_THIS_DOES 223 #define ISIOVA(va) \ 224 ((char *)(va) >= iobase && (char *)(va) < iolimit) 225 #define IOV(pa) ((int)(pa)-IOBASE+(int)iobase) 226 #define IOP(va) ((int)(va)-(int)iobase+IOBASE) 227 #define IOPOFF(pa) ((int)(pa)-IOBASE) 228 #define IOMAPSIZE btoc(IOTOP-IOBASE) 229 #endif 230 231 /* 232 ALICE 05/24/92,13:25:19 BG -- We need to make sure to map NuBus memory in 233 the kernel, too. 234 ALICE 06/29/92,20:40:00 LK -- I did that, thank you very much. Been there. 235 */ 236 237 238 /* 239 * 68851 and 68030 MMU 240 */ 241 #define PMMU_LVLMASK 0x0007 242 #define PMMU_INV 0x0400 243 #define PMMU_WP 0x0800 244 #define PMMU_ALV 0x1000 245 #define PMMU_SO 0x2000 246 #define PMMU_LV 0x4000 247 #define PMMU_BE 0x8000 248 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 249 250 /* 680X0 function codes */ 251 #define FC_USERD 1 /* user data space */ 252 #define FC_USERP 2 /* user program space */ 253 #define FC_SUPERD 5 /* supervisor data space */ 254 #define FC_SUPERP 6 /* supervisor program space */ 255 #define FC_CPU 7 /* CPU space */ 256 257 /* fields in the 68020 cache control register */ 258 #define IC_ENABLE 0x0001 /* enable instruction cache */ 259 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 260 #define IC_CE 0x0004 /* clear instruction cache entry */ 261 #define IC_CLR 0x0008 /* clear entire instruction cache */ 262 263 /* additional fields in the 68030 cache control register */ 264 #define IC_BE 0x0010 /* instruction burst enable */ 265 #define DC_ENABLE 0x0100 /* data cache enable */ 266 #define DC_FREEZE 0x0200 /* data cache freeze */ 267 #define DC_CE 0x0400 /* clear data cache entry */ 268 #define DC_CLR 0x0800 /* clear entire data cache */ 269 #define DC_BE 0x1000 /* data burst enable */ 270 #define DC_WA 0x2000 /* write allocate */ 271 272 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 273 #define CACHE_OFF (DC_CLR|IC_CLR) 274 #define CACHE_CLR (CACHE_ON) 275 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 276 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 277