1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved. 41 * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot 42 43 * Redistribution of this source code or any part thereof is permitted, 44 * provided that the following conditions are met: 45 * 1) Utilized source contains the copyright message above, this list 46 * of conditions, and the following disclaimer. 47 * 2) Binary objects containing compiled source reproduce the 48 * copyright notice above on startup. 49 * 50 * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any 51 * warranties of ANY kind are disclaimed. We don't even claim that it 52 * won't crash your hard disk. Basically, we want a little credit if 53 * it works, but we don't want to get mail-bombed if it doesn't. 54 */ 55 56 /* 57 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 58 * 59 * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91 60 * $Id: cpu.h,v 1.2 1993/11/29 00:37:59 briggs Exp $ 61 */ 62 63 /* 64 ALICE 65 BG -- Sat May 23 23:58:23 EDT 1992 66 Exported defines and stuff unique to macII/68k. 67 */ 68 69 /* 70 * definitions of cpu-dependent requirements 71 * referenced in generic code 72 */ 73 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 74 75 /* 76 * function vs. inline configuration; 77 * these are defined to get generic functions 78 * rather than inline or machine-dependent implementations 79 */ 80 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 81 #undef NEED_FFS /* don't need ffs function */ 82 #undef NEED_BCMP /* don't need bcmp function */ 83 #undef NEED_STRLEN /* don't need strlen function */ 84 85 /* ALICE BG -- Sun May 24 11:31:35 EDT 1992 -- what the hell do these things */ 86 /* do? */ 87 #define cpu_exec(p) /* nothing */ 88 #define cpu_wait(p) /* nothing */ 89 90 /* 91 * Arguments to hardclock, softclock and gatherstats 92 * encapsulate the previous machine state in an opaque 93 * clockframe; for hp300, use just what the hardware 94 * leaves on the stack. 95 */ 96 /* ALICE 05/23/92 BG -- Oh, no. What does a VIA intleave on the stack? */ 97 /* ALICE 06/27/92 LK -- Make sure hardware clock routine does this: */ 98 99 typedef struct intrframe { 100 int pc; 101 int ps; 102 } clockframe; 103 104 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 105 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 106 #define CLKF_PC(framep) ((framep)->pc) 107 108 /* 109 * Preempt the current process if in interrupt from user mode, 110 * or after the current trap/syscall if in system mode. 111 */ 112 #define need_resched() { want_resched++; aston(); } 113 114 /* 115 * Give a profiling tick to the current process from the softclock 116 * interrupt. Request an ast to send us through trap(), 117 * marking the proc as needing a profiling tick. 118 */ 119 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 120 121 /* 122 * Notify the current process (p) that it has a signal pending, 123 * process as soon as possible. 124 */ 125 #define signotify(p) aston() 126 127 #define aston() (astpending++) 128 129 int astpending; /* need to trap before returning to user mode */ 130 int want_resched; /* resched() was called */ 131 132 /* XXX why is this duplicated in mtpr.h? brad@fcr.com */ 133 /* 134 * simulated software interrupt register 135 */ 136 extern unsigned char ssir; 137 138 #define SIR_NET 0x1 139 #define SIR_CLOCK 0x2 140 #define SIR_SERIAL 0x4 141 142 #define siroff(x) ssir &= ~(x) 143 #define setsoftnet() ssir |= SIR_NET 144 #define setsoftclock() ssir |= SIR_CLOCK 145 #define setsoftserial() ssir |= SIR_SERIAL 146 147 148 149 /* 150 * The rest of this should probably be moved to ../macII/macIIcpu.h, 151 * although some of it could probably be put into generic 68k headers. 152 */ 153 154 /* values for machineid */ 155 /* BARF MF - some values from the thinkc gesalt include file */ 156 #define MACH_MAC2 6 157 #define MACH_MAC2X 7 158 #define MACH_MAC2SI 18 159 #define MACH_MAC2CI 11 160 #define MACH_MAC2CX 8 161 #define MACH_MACSE30 9 162 #define MACH_MAC2FX 13 163 164 /* MF processor passed in */ 165 #define MACH_68020 0 166 #define MACH_68030 1 167 #define MACH_68040 2 168 #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */ 169 170 /* values for cpuspeed (not really related to clock speed due to caches) */ 171 #define MHZ_8 1 172 #define MHZ_16 2 173 #define MHZ_25 3 174 #define MHZ_33 4 175 #define MHZ_40 5 176 177 #ifdef KERNEL 178 extern int machineid, ectype; 179 extern char *intiobase, *intiolimit; 180 extern char *extiobase, *extiolimit; 181 182 #endif 183 184 /* physical memory sections */ 185 #define ROMBASE (0x40000000) 186 #define IOBASE (0x50000000) 187 #define INTIOBASE IOBASE 188 #define IOTOP (0x51000000) /* ~ 128 K */ 189 #define IOMAPSIZE btoc(IOTOP - IOBASE) 190 191 /* ALICE 05/23/92 BG -- These need to be changed. */ 192 #ifdef NO_SUPER_SPACE_YET 193 #define NBSBASE 0x60000000 /* NUBUS Super space */ 194 #define NBSTOP 0xF0000000 195 #endif 196 #define NBBASE 0xF9000000 /* NUBUS space */ 197 #define NBTOP 0xFF000000 /* NUBUS space */ 198 #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */ 199 #define NBMEMSIZE 0x01000000 /* 16 megs per card */ 200 #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */ 201 202 /* 203 * IO space: 204 * 205 * Internal IO space is mapped in the kernel from ``intiobase'' to 206 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 207 * conversion between physical and kernel virtual addresses is easy. 208 */ 209 #define ISIIOVA(va) \ 210 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 211 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 212 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 213 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 214 215 /* 216 ALICE 05/24/92,13:25:19 BG -- We need to make sure to map NuBus memory in 217 the kernel, too. 218 ALICE 06/29/92,20:40:00 LK -- I did that, thank you very much. Been there. 219 */ 220 221 222 /* 223 * 68851 and 68030 MMU 224 */ 225 #define PMMU_LVLMASK 0x0007 226 #define PMMU_INV 0x0400 227 #define PMMU_WP 0x0800 228 #define PMMU_ALV 0x1000 229 #define PMMU_SO 0x2000 230 #define PMMU_LV 0x4000 231 #define PMMU_BE 0x8000 232 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 233 234 /* 680X0 function codes */ 235 #define FC_USERD 1 /* user data space */ 236 #define FC_USERP 2 /* user program space */ 237 #define FC_SUPERD 5 /* supervisor data space */ 238 #define FC_SUPERP 6 /* supervisor program space */ 239 #define FC_CPU 7 /* CPU space */ 240 241 /* fields in the 68020 cache control register */ 242 #define IC_ENABLE 0x0001 /* enable instruction cache */ 243 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 244 #define IC_CE 0x0004 /* clear instruction cache entry */ 245 #define IC_CLR 0x0008 /* clear entire instruction cache */ 246 247 /* additional fields in the 68030 cache control register */ 248 #define IC_BE 0x0010 /* instruction burst enable */ 249 #define DC_ENABLE 0x0100 /* data cache enable */ 250 #define DC_FREEZE 0x0200 /* data cache freeze */ 251 #define DC_CE 0x0400 /* clear data cache entry */ 252 #define DC_CLR 0x0800 /* clear entire data cache */ 253 #define DC_BE 0x1000 /* data burst enable */ 254 #define DC_WA 0x2000 /* write allocate */ 255 256 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 257 #define CACHE_OFF (DC_CLR|IC_CLR) 258 #define CACHE_CLR (CACHE_ON) 259 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 260 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 261