1 /* $NetBSD: sbc.c,v 1.38 1998/11/19 21:46:24 thorpej Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 #include "opt_ddb.h" 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsipi_debug.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/ncr5380reg.h> 64 #include <dev/ic/ncr5380var.h> 65 66 #include <machine/cpu.h> 67 #include <machine/viareg.h> 68 69 #include <mac68k/dev/sbcreg.h> 70 #include <mac68k/dev/sbcvar.h> 71 72 /* SBC_DEBUG -- relies on DDB */ 73 #ifdef SBC_DEBUG 74 # define SBC_DB_INTR 0x01 75 # define SBC_DB_DMA 0x02 76 # define SBC_DB_REG 0x04 77 # define SBC_DB_BREAK 0x08 78 # ifndef DDB 79 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 80 # endif 81 # define SBC_BREAK \ 82 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 83 #else 84 # define SBC_BREAK 85 #endif 86 87 88 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 89 int sbc_link_flags = 0 /* | SDEV_DB2 */; 90 int sbc_options = 0 /* | SBC_PDMA */; 91 92 /* This is copied from julian's bt driver */ 93 /* "so we have a default dev struct for our link struct." */ 94 struct scsipi_device sbc_dev = { 95 NULL, /* Use default error handler. */ 96 NULL, /* Use default start handler. */ 97 NULL, /* Use default async handler. */ 98 NULL, /* Use default "done" routine. */ 99 }; 100 101 extern label_t *nofault; 102 extern caddr_t m68k_fault_addr; 103 104 static int sbc_wait_busy __P((struct ncr5380_softc *)); 105 static int sbc_ready __P((struct ncr5380_softc *)); 106 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 107 108 109 /*** 110 * General support for Mac-specific SCSI logic. 111 ***/ 112 113 /* These are used in the following inline functions. */ 114 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 115 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 116 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 117 118 /* Return zero on success. */ 119 static __inline__ int 120 sbc_wait_busy(sc) 121 struct ncr5380_softc *sc; 122 { 123 int timo = sbc_wait_busy_timo; 124 for (;;) { 125 if (SCI_BUSY(sc)) { 126 timo = 0; /* return 0 */ 127 break; 128 } 129 if (--timo < 0) 130 break; /* return -1 */ 131 delay(2); 132 } 133 return (timo); 134 } 135 136 static __inline__ int 137 sbc_ready(sc) 138 struct ncr5380_softc *sc; 139 { 140 int timo = sbc_ready_timo; 141 142 for (;;) { 143 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 144 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 145 timo = 0; 146 break; 147 } 148 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 149 || (SCI_BUSY(sc) == 0)) { 150 timo = -1; 151 break; 152 } 153 if (--timo < 0) 154 break; /* return -1 */ 155 delay(2); 156 } 157 return (timo); 158 } 159 160 static __inline__ int 161 sbc_wait_dreq(sc) 162 struct ncr5380_softc *sc; 163 { 164 int timo = sbc_wait_dreq_timo; 165 166 for (;;) { 167 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 168 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 169 timo = 0; 170 break; 171 } 172 if (--timo < 0) 173 break; /* return -1 */ 174 delay(2); 175 } 176 return (timo); 177 } 178 179 void 180 sbc_irq_intr(p) 181 void *p; 182 { 183 struct ncr5380_softc *ncr_sc = p; 184 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 185 int claimed = 0; 186 extern int cold; 187 188 /* How we ever arrive here without IRQ set is a mystery... */ 189 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 190 #ifdef SBC_DEBUG 191 if (sbc_debug & SBC_DB_INTR) 192 decode_5380_intr(ncr_sc); 193 #endif 194 if (!cold) 195 claimed = ncr5380_intr(ncr_sc); 196 if (!claimed) { 197 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 198 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 199 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 200 if (sc->sc_clrintr) 201 (*sc->sc_clrintr)(ncr_sc); 202 } 203 #ifdef SBC_DEBUG 204 else { 205 printf("%s: spurious intr\n", 206 ncr_sc->sc_dev.dv_xname); 207 SBC_BREAK; 208 } 209 #endif 210 } 211 } 212 } 213 214 #ifdef SBC_DEBUG 215 void 216 decode_5380_intr(ncr_sc) 217 struct ncr5380_softc *ncr_sc; 218 { 219 u_int8_t csr = *ncr_sc->sci_csr; 220 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 221 222 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 223 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 224 if (csr & SCI_BUS_IO) 225 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 226 else 227 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 228 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 229 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 230 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 231 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 232 ((bus_csr & ~SCI_BUS_RST) == 0)) 233 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 234 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 235 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 236 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 237 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 238 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 239 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 240 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 241 (bus_csr == 0)) 242 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 243 else 244 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 245 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 246 } 247 #endif 248 249 250 /*** 251 * The following code implements polled PDMA. 252 ***/ 253 254 int 255 sbc_pdma_in(ncr_sc, phase, datalen, data) 256 struct ncr5380_softc *ncr_sc; 257 int phase; 258 int datalen; 259 u_char *data; 260 { 261 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 262 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 263 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 264 int resid, s; 265 266 if (datalen < ncr_sc->sc_min_dma_len || 267 (sc->sc_options & SBC_PDMA) == 0) 268 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 269 270 s = splbio(); 271 if (sbc_wait_busy(ncr_sc)) { 272 splx(s); 273 return 0; 274 } 275 276 *ncr_sc->sci_mode |= SCI_MODE_DMA; 277 *ncr_sc->sci_irecv = 0; 278 279 #define R4 *((u_int32_t *)data)++ = *long_data 280 #define R1 *((u_int8_t *)data)++ = *byte_data 281 for (resid = datalen; resid >= 128; resid -= 128) { 282 if (sbc_ready(ncr_sc)) 283 goto interrupt; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; 286 R4; R4; R4; R4; R4; R4; R4; R4; 287 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 288 } 289 while (resid) { 290 if (sbc_ready(ncr_sc)) 291 goto interrupt; 292 R1; 293 resid--; 294 } 295 #undef R4 296 #undef R1 297 298 interrupt: 299 SCI_CLR_INTR(ncr_sc); 300 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 301 *ncr_sc->sci_icmd = 0; 302 splx(s); 303 return (datalen - resid); 304 } 305 306 int 307 sbc_pdma_out(ncr_sc, phase, datalen, data) 308 struct ncr5380_softc *ncr_sc; 309 int phase; 310 int datalen; 311 u_char *data; 312 { 313 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 314 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 315 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 316 label_t faultbuf; 317 int resid, s; 318 u_int8_t icmd; 319 320 #if 1 321 /* Work around lame gcc initialization bug */ 322 (void)&data; 323 #endif 324 325 if (datalen < ncr_sc->sc_min_dma_len || 326 (sc->sc_options & SBC_PDMA) == 0) 327 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 328 329 s = splbio(); 330 if (sbc_wait_busy(ncr_sc)) { 331 splx(s); 332 return 0; 333 } 334 335 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 336 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 337 *ncr_sc->sci_mode |= SCI_MODE_DMA; 338 *ncr_sc->sci_dma_send = 0; 339 340 /* 341 * Setup for a possible bus error caused by SCSI controller 342 * switching out of DATA OUT before we're done with the 343 * current transfer. (See comment before sbc_drq_intr().) 344 */ 345 nofault = &faultbuf; 346 347 if (setjmp(nofault)) { 348 printf("buf = 0x%lx, fault = 0x%lx\n", 349 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 350 panic("Unexpected bus error in sbc_pdma_out()"); 351 } 352 353 #define W1 *byte_data = *((u_int8_t *)data)++ 354 #define W4 *long_data = *((u_int32_t *)data)++ 355 for (resid = datalen; resid >= 64; resid -= 64) { 356 if (sbc_ready(ncr_sc)) 357 goto interrupt; 358 W1; 359 if (sbc_ready(ncr_sc)) 360 goto interrupt; 361 W1; 362 if (sbc_ready(ncr_sc)) 363 goto interrupt; 364 W1; 365 if (sbc_ready(ncr_sc)) 366 goto interrupt; 367 W1; 368 if (sbc_ready(ncr_sc)) 369 goto interrupt; 370 W4; W4; W4; W4; 371 W4; W4; W4; W4; 372 W4; W4; W4; W4; 373 W4; W4; W4; 374 } 375 while (resid) { 376 if (sbc_ready(ncr_sc)) 377 goto interrupt; 378 W1; 379 resid--; 380 } 381 #undef W1 382 #undef W4 383 if (sbc_wait_dreq(ncr_sc)) 384 printf("%s: timeout waiting for DREQ.\n", 385 ncr_sc->sc_dev.dv_xname); 386 387 *byte_data = 0; 388 goto done; 389 390 interrupt: 391 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 392 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 393 --resid; 394 } 395 396 done: 397 SCI_CLR_INTR(ncr_sc); 398 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 399 *ncr_sc->sci_icmd = icmd; 400 splx(s); 401 return (datalen - resid); 402 } 403 404 405 /*** 406 * The following code implements interrupt-driven PDMA. 407 ***/ 408 409 /* 410 * This is the meat of the PDMA transfer. 411 * When we get here, we shove data as fast as the mac can take it. 412 * We depend on several things: 413 * * All macs after the Mac Plus that have a 5380 chip should have a general 414 * logic IC that handshakes data for blind transfers. 415 * * If the SCSI controller finishes sending/receiving data before we do, 416 * the same general logic IC will generate a /BERR for us in short order. 417 * * The fault address for said /BERR minus the base address for the 418 * transfer will be the amount of data that was actually written. 419 * 420 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 421 * detect and handle the bus error for early termination of a command. 422 * This is usually caused by a disconnecting target. 423 */ 424 void 425 sbc_drq_intr(p) 426 void *p; 427 { 428 struct sbc_softc *sc = (struct sbc_softc *)p; 429 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 430 struct sci_req *sr = ncr_sc->sc_current; 431 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 432 label_t faultbuf; 433 volatile u_int32_t *long_drq; 434 u_int32_t *long_data; 435 volatile u_int8_t *drq; 436 u_int8_t *data; 437 int count, dcount, resid; 438 u_int8_t tmp; 439 440 /* Work around lame gcc initialization bug */ 441 (void)&drq; 442 443 /* 444 * If we're not ready to xfer data, or have no more, just return. 445 */ 446 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 447 return; 448 449 #ifdef SBC_DEBUG 450 if (sbc_debug & SBC_DB_INTR) 451 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 452 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 453 #endif 454 455 /* 456 * Setup for a possible bus error caused by SCSI controller 457 * switching out of DATA-IN/OUT before we're done with the 458 * current transfer. 459 */ 460 nofault = &faultbuf; 461 462 if (setjmp(nofault)) { 463 nofault = (label_t *)0; 464 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 465 count = (( (u_long)m68k_fault_addr 466 - (u_long)sc->sc_drq_addr)); 467 468 if ((count < 0) || (count > dh->dh_len)) { 469 printf("%s: complete=0x%x (pending 0x%x)\n", 470 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 471 panic("something is wrong"); 472 } 473 474 dh->dh_addr += count; 475 dh->dh_len -= count; 476 } else 477 count = 0; 478 479 #ifdef SBC_DEBUG 480 if (sbc_debug & SBC_DB_INTR) 481 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 482 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 483 #endif 484 m68k_fault_addr = 0; 485 486 return; 487 } 488 489 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 490 dcount = 0; 491 492 /* 493 * Get the source address aligned. 494 */ 495 resid = 496 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 497 if (count && count < 4) { 498 drq = (volatile u_int8_t *)sc->sc_drq_addr; 499 data = (u_int8_t *)dh->dh_addr; 500 501 #define W1 *drq++ = *data++ 502 while (count) { 503 W1; count--; 504 } 505 #undef W1 506 dh->dh_addr += resid; 507 dh->dh_len -= resid; 508 } 509 510 /* 511 * Start the transfer. 512 */ 513 while (dh->dh_len) { 514 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 515 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 516 long_data = (u_int32_t *)dh->dh_addr; 517 518 #define W4 *long_drq++ = *long_data++ 519 while (count >= 64) { 520 W4; W4; W4; W4; W4; W4; W4; W4; 521 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 522 count -= 64; 523 } 524 while (count >= 4) { 525 W4; count -= 4; 526 } 527 #undef W4 528 data = (u_int8_t *)long_data; 529 drq = (u_int8_t *)long_drq; 530 531 #define W1 *drq++ = *data++ 532 while (count) { 533 W1; count--; 534 } 535 #undef W1 536 dh->dh_len -= dcount; 537 dh->dh_addr += dcount; 538 } 539 dh->dh_flags |= SBC_DH_DONE; 540 541 /* 542 * XXX -- Read a byte from the SBC to trigger a /BERR. 543 * This seems to be necessary for us to notice that 544 * the target has disconnected. Ick. 06 jun 1996 (sr) 545 */ 546 if (dcount >= MAX_DMA_LEN) 547 drq = (volatile u_int8_t *)sc->sc_drq_addr; 548 tmp = *drq; 549 } else { /* Data In */ 550 /* 551 * Get the dest address aligned. 552 */ 553 resid = 554 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 555 if (count && count < 4) { 556 data = (u_int8_t *)dh->dh_addr; 557 drq = (volatile u_int8_t *)sc->sc_drq_addr; 558 559 #define R1 *data++ = *drq++ 560 while (count) { 561 R1; count--; 562 } 563 #undef R1 564 dh->dh_addr += resid; 565 dh->dh_len -= resid; 566 } 567 568 /* 569 * Start the transfer. 570 */ 571 while (dh->dh_len) { 572 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 573 long_data = (u_int32_t *)dh->dh_addr; 574 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 575 576 #define R4 *long_data++ = *long_drq++ 577 while (count >= 64) { 578 R4; R4; R4; R4; R4; R4; R4; R4; 579 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 580 count -= 64; 581 } 582 while (count >= 4) { 583 R4; count -= 4; 584 } 585 #undef R4 586 data = (u_int8_t *)long_data; 587 drq = (volatile u_int8_t *)long_drq; 588 589 #define R1 *data++ = *drq++ 590 while (count) { 591 R1; count--; 592 } 593 #undef R1 594 dh->dh_len -= dcount; 595 dh->dh_addr += dcount; 596 } 597 dh->dh_flags |= SBC_DH_DONE; 598 } 599 600 /* 601 * OK. No bus error occurred above. Clear the nofault flag 602 * so we no longer short-circuit bus errors. 603 */ 604 nofault = (label_t *)0; 605 606 #ifdef SBC_DEBUG 607 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 608 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 609 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 610 *ncr_sc->sci_bus_csr); 611 #endif 612 } 613 614 void 615 sbc_dma_alloc(ncr_sc) 616 struct ncr5380_softc *ncr_sc; 617 { 618 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 619 struct sci_req *sr = ncr_sc->sc_current; 620 struct scsipi_xfer *xs = sr->sr_xs; 621 struct sbc_pdma_handle *dh; 622 int i, xlen; 623 624 #ifdef DIAGNOSTIC 625 if (sr->sr_dma_hand != NULL) 626 panic("sbc_dma_alloc: already have PDMA handle"); 627 #endif 628 629 /* Polled transfers shouldn't allocate a PDMA handle. */ 630 if (sr->sr_flags & SR_IMMED) 631 return; 632 633 xlen = ncr_sc->sc_datalen; 634 635 /* Make sure our caller checked sc_min_dma_len. */ 636 if (xlen < MIN_DMA_LEN) 637 panic("sbc_dma_alloc: len=0x%x\n", xlen); 638 639 /* 640 * Find free PDMA handle. Guaranteed to find one since we 641 * have as many PDMA handles as the driver has processes. 642 * (instances?) 643 */ 644 for (i = 0; i < SCI_OPENINGS; i++) { 645 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 646 goto found; 647 } 648 panic("sbc: no free PDMA handles"); 649 found: 650 dh = &sc->sc_pdma[i]; 651 dh->dh_flags = SBC_DH_BUSY; 652 dh->dh_addr = ncr_sc->sc_dataptr; 653 dh->dh_len = xlen; 654 655 /* Copy the 'write' flag for convenience. */ 656 if (xs->flags & SCSI_DATA_OUT) 657 dh->dh_flags |= SBC_DH_OUT; 658 659 sr->sr_dma_hand = dh; 660 } 661 662 void 663 sbc_dma_free(ncr_sc) 664 struct ncr5380_softc *ncr_sc; 665 { 666 struct sci_req *sr = ncr_sc->sc_current; 667 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 668 669 #ifdef DIAGNOSTIC 670 if (sr->sr_dma_hand == NULL) 671 panic("sbc_dma_free: no DMA handle"); 672 #endif 673 674 if (ncr_sc->sc_state & NCR_DOINGDMA) 675 panic("sbc_dma_free: free while in progress"); 676 677 if (dh->dh_flags & SBC_DH_BUSY) { 678 dh->dh_flags = 0; 679 dh->dh_addr = NULL; 680 dh->dh_len = 0; 681 } 682 sr->sr_dma_hand = NULL; 683 } 684 685 void 686 sbc_dma_poll(ncr_sc) 687 struct ncr5380_softc *ncr_sc; 688 { 689 struct sci_req *sr = ncr_sc->sc_current; 690 691 /* 692 * We shouldn't arrive here; if SR_IMMED is set, then 693 * dma_alloc() should have refused to allocate a handle 694 * for the transfer. This forces the polled PDMA code 695 * to handle the request... 696 */ 697 #ifdef SBC_DEBUG 698 if (sbc_debug & SBC_DB_DMA) 699 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 700 #endif 701 sr->sr_flags |= SR_OVERDUE; 702 } 703 704 void 705 sbc_dma_setup(ncr_sc) 706 struct ncr5380_softc *ncr_sc; 707 { 708 /* Not needed; we don't have real DMA */ 709 } 710 711 void 712 sbc_dma_start(ncr_sc) 713 struct ncr5380_softc *ncr_sc; 714 { 715 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 716 struct sci_req *sr = ncr_sc->sc_current; 717 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 718 719 /* 720 * Match bus phase, clear pending interrupts, set DMA mode, and 721 * assert data bus (for writing only), then start the transfer. 722 */ 723 if (dh->dh_flags & SBC_DH_OUT) { 724 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 725 SCI_CLR_INTR(ncr_sc); 726 if (sc->sc_clrintr) 727 (*sc->sc_clrintr)(ncr_sc); 728 *ncr_sc->sci_mode |= SCI_MODE_DMA; 729 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 730 *ncr_sc->sci_dma_send = 0; 731 } else { 732 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 733 SCI_CLR_INTR(ncr_sc); 734 if (sc->sc_clrintr) 735 (*sc->sc_clrintr)(ncr_sc); 736 *ncr_sc->sci_mode |= SCI_MODE_DMA; 737 *ncr_sc->sci_icmd = 0; 738 *ncr_sc->sci_irecv = 0; 739 } 740 ncr_sc->sc_state |= NCR_DOINGDMA; 741 742 #ifdef SBC_DEBUG 743 if (sbc_debug & SBC_DB_DMA) 744 printf("%s: PDMA started, va=%p, len=0x%x\n", 745 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 746 #endif 747 } 748 749 void 750 sbc_dma_eop(ncr_sc) 751 struct ncr5380_softc *ncr_sc; 752 { 753 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 754 } 755 756 void 757 sbc_dma_stop(ncr_sc) 758 struct ncr5380_softc *ncr_sc; 759 { 760 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 761 struct sci_req *sr = ncr_sc->sc_current; 762 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 763 int ntrans; 764 765 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 766 #ifdef SBC_DEBUG 767 if (sbc_debug & SBC_DB_DMA) 768 printf("%s: dma_stop: DMA not running\n", 769 ncr_sc->sc_dev.dv_xname); 770 #endif 771 return; 772 } 773 ncr_sc->sc_state &= ~NCR_DOINGDMA; 774 775 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 776 ntrans = ncr_sc->sc_datalen - dh->dh_len; 777 778 #ifdef SBC_DEBUG 779 if (sbc_debug & SBC_DB_DMA) 780 printf("%s: dma_stop: ntrans=0x%x\n", 781 ncr_sc->sc_dev.dv_xname, ntrans); 782 #endif 783 784 if (ntrans > ncr_sc->sc_datalen) 785 panic("sbc_dma_stop: excess transfer\n"); 786 787 /* Adjust data pointer */ 788 ncr_sc->sc_dataptr += ntrans; 789 ncr_sc->sc_datalen -= ntrans; 790 791 /* Clear any pending interrupts. */ 792 SCI_CLR_INTR(ncr_sc); 793 if (sc->sc_clrintr) 794 (*sc->sc_clrintr)(ncr_sc); 795 } 796 797 /* Put SBIC back into PIO mode. */ 798 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 799 *ncr_sc->sci_icmd = 0; 800 801 #ifdef SBC_DEBUG 802 if (sbc_debug & SBC_DB_REG) 803 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 804 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 805 *ncr_sc->sci_bus_csr); 806 #endif 807 } 808