1 /* $NetBSD: sbc.c,v 1.55 2012/12/07 08:04:02 hauke Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.55 2012/12/07 08:04:02 hauke Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsipi_debug.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/ic/ncr5380reg.h> 67 #include <dev/ic/ncr5380var.h> 68 69 #include <machine/cpu.h> 70 #include <machine/viareg.h> 71 72 #include <mac68k/dev/sbcreg.h> 73 #include <mac68k/dev/sbcvar.h> 74 75 /* SBC_DEBUG -- relies on DDB */ 76 #ifdef SBC_DEBUG 77 # define SBC_DB_INTR 0x01 78 # define SBC_DB_DMA 0x02 79 # define SBC_DB_REG 0x04 80 # define SBC_DB_BREAK 0x08 81 # ifndef DDB 82 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 83 # endif 84 # define SBC_BREAK \ 85 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 86 #else 87 # define SBC_BREAK 88 #endif 89 90 91 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 92 int sbc_link_flags = 0 /* | SDEV_DB2 */; 93 int sbc_options = 0 /* | SBC_PDMA */; 94 95 extern label_t *nofault; 96 extern void * m68k_fault_addr; 97 98 static int sbc_wait_busy(struct ncr5380_softc *); 99 static int sbc_ready(struct ncr5380_softc *); 100 static int sbc_wait_dreq(struct ncr5380_softc *); 101 102 103 /*** 104 * General support for Mac-specific SCSI logic. 105 ***/ 106 107 /* These are used in the following inline functions. */ 108 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 109 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 111 112 /* Return zero on success. */ 113 static inline int 114 sbc_wait_busy(struct ncr5380_softc *sc) 115 { 116 int timo = sbc_wait_busy_timo; 117 for (;;) { 118 if (SCI_BUSY(sc)) { 119 timo = 0; /* return 0 */ 120 break; 121 } 122 if (--timo < 0) 123 break; /* return -1 */ 124 delay(2); 125 } 126 return (timo); 127 } 128 129 static inline int 130 sbc_ready(struct ncr5380_softc *sc) 131 { 132 int timo = sbc_ready_timo; 133 134 for (;;) { 135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 136 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 137 timo = 0; 138 break; 139 } 140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 141 || (SCI_BUSY(sc) == 0)) { 142 timo = -1; 143 break; 144 } 145 if (--timo < 0) 146 break; /* return -1 */ 147 delay(2); 148 } 149 return (timo); 150 } 151 152 static inline int 153 sbc_wait_dreq(struct ncr5380_softc *sc) 154 { 155 int timo = sbc_wait_dreq_timo; 156 157 for (;;) { 158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 160 timo = 0; 161 break; 162 } 163 if (--timo < 0) 164 break; /* return -1 */ 165 delay(2); 166 } 167 return (timo); 168 } 169 170 void 171 sbc_irq_intr(void *p) 172 { 173 struct ncr5380_softc *ncr_sc = p; 174 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 175 int claimed = 0; 176 177 /* How we ever arrive here without IRQ set is a mystery... */ 178 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 179 #ifdef SBC_DEBUG 180 if (sbc_debug & SBC_DB_INTR) 181 decode_5380_intr(ncr_sc); 182 #endif 183 if (!cold) 184 claimed = ncr5380_intr(ncr_sc); 185 if (!claimed) { 186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 187 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 188 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 189 if (sc->sc_clrintr) 190 (*sc->sc_clrintr)(ncr_sc); 191 } 192 #ifdef SBC_DEBUG 193 else { 194 printf("%s: spurious intr\n", 195 device_xname(ncr_sc->sc_dev)); 196 SBC_BREAK; 197 } 198 #endif 199 } 200 } 201 } 202 203 #ifdef SBC_DEBUG 204 void 205 decode_5380_intr(struct ncr5380_softc *ncr_sc) 206 { 207 u_int8_t csr = *ncr_sc->sci_csr; 208 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 209 210 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 211 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 212 if (csr & SCI_BUS_IO) 213 printf("%s: reselect\n", device_xname(ncr_sc->sc_dev)); 214 else 215 printf("%s: select\n", device_xname(ncr_sc->sc_dev)); 216 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 217 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 218 printf("%s: DMA eop\n", device_xname(ncr_sc->sc_dev)); 219 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 220 ((bus_csr & ~SCI_BUS_RST) == 0)) 221 printf("%s: bus reset\n", device_xname(ncr_sc->sc_dev)); 222 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 223 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 224 printf("%s: parity error\n", device_xname(ncr_sc->sc_dev)); 225 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 226 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 227 printf("%s: phase mismatch\n", device_xname(ncr_sc->sc_dev)); 228 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 229 (bus_csr == 0)) 230 printf("%s: disconnect\n", device_xname(ncr_sc->sc_dev)); 231 else 232 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 233 device_xname(ncr_sc->sc_dev), csr, bus_csr); 234 } 235 #endif 236 237 238 /*** 239 * The following code implements polled PDMA. 240 ***/ 241 242 int 243 sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 244 { 245 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 246 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 247 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 248 label_t faultbuf; 249 int resid, s; 250 251 if (datalen < ncr_sc->sc_min_dma_len || 252 (sc->sc_options & SBC_PDMA) == 0) 253 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 254 255 s = splbio(); 256 if (sbc_wait_busy(ncr_sc)) { 257 splx(s); 258 return 0; 259 } 260 261 *ncr_sc->sci_mode |= SCI_MODE_DMA; 262 *ncr_sc->sci_irecv = 0; 263 264 resid = datalen; 265 266 /* 267 * Setup for a possible bus error caused by SCSI controller 268 * switching out of DATA OUT before we're done with the 269 * current transfer. (See comment before sbc_drq_intr().) 270 */ 271 nofault = &faultbuf; 272 if (setjmp(nofault)) { 273 goto interrupt; 274 } 275 276 #define R4 *(u_int32_t *)data = *long_data, data += 4; 277 for (; resid >= 128; resid -= 128) { 278 if (sbc_ready(ncr_sc)) 279 goto interrupt; 280 R4; R4; R4; R4; R4; R4; R4; R4; 281 R4; R4; R4; R4; R4; R4; R4; R4; 282 R4; R4; R4; R4; R4; R4; R4; R4; 283 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 284 } 285 while (resid) { 286 if (sbc_ready(ncr_sc)) 287 goto interrupt; 288 *(u_int8_t *)data = *byte_data, data += 1; 289 resid--; 290 } 291 #undef R4 292 293 interrupt: 294 nofault = NULL; 295 SCI_CLR_INTR(ncr_sc); 296 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 297 *ncr_sc->sci_icmd = 0; 298 splx(s); 299 return (datalen - resid); 300 } 301 302 int 303 sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 304 { 305 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 306 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 307 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 308 label_t faultbuf; 309 int resid, s; 310 u_int8_t icmd; 311 312 #if 1 313 /* Work around lame gcc initialization bug */ 314 (void)&data; 315 #endif 316 317 if (datalen < ncr_sc->sc_min_dma_len || 318 (sc->sc_options & SBC_PDMA) == 0) 319 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 320 321 s = splbio(); 322 if (sbc_wait_busy(ncr_sc)) { 323 splx(s); 324 return 0; 325 } 326 327 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 328 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 329 *ncr_sc->sci_mode |= SCI_MODE_DMA; 330 *ncr_sc->sci_dma_send = 0; 331 332 /* 333 * Setup for a possible bus error caused by SCSI controller 334 * switching out of DATA OUT before we're done with the 335 * current transfer. (See comment before sbc_drq_intr().) 336 */ 337 nofault = &faultbuf; 338 339 if (setjmp(nofault)) { 340 printf("buf = 0x%lx, fault = 0x%lx\n", 341 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 342 panic("Unexpected bus error in sbc_pdma_out()"); 343 } 344 345 #define W1 *byte_data = *(u_int8_t *)data, data += 1 346 #define W4 *long_data = *(u_int32_t *)data, data += 4 347 for (resid = datalen; resid >= 64; resid -= 64) { 348 if (sbc_ready(ncr_sc)) 349 goto interrupt; 350 W1; 351 if (sbc_ready(ncr_sc)) 352 goto interrupt; 353 W1; 354 if (sbc_ready(ncr_sc)) 355 goto interrupt; 356 W1; 357 if (sbc_ready(ncr_sc)) 358 goto interrupt; 359 W1; 360 if (sbc_ready(ncr_sc)) 361 goto interrupt; 362 W4; W4; W4; W4; 363 W4; W4; W4; W4; 364 W4; W4; W4; W4; 365 W4; W4; W4; 366 } 367 while (resid) { 368 if (sbc_ready(ncr_sc)) 369 goto interrupt; 370 W1; 371 resid--; 372 } 373 #undef W1 374 #undef W4 375 if (sbc_wait_dreq(ncr_sc)) 376 printf("%s: timeout waiting for DREQ.\n", 377 device_xname(ncr_sc->sc_dev)); 378 379 *byte_data = 0; 380 goto done; 381 382 interrupt: 383 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 384 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 385 --resid; 386 } 387 388 done: 389 SCI_CLR_INTR(ncr_sc); 390 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 391 *ncr_sc->sci_icmd = icmd; 392 splx(s); 393 return (datalen - resid); 394 } 395 396 397 /*** 398 * The following code implements interrupt-driven PDMA. 399 ***/ 400 401 /* 402 * This is the meat of the PDMA transfer. 403 * When we get here, we shove data as fast as the mac can take it. 404 * We depend on several things: 405 * * All macs after the Mac Plus that have a 5380 chip should have a general 406 * logic IC that handshakes data for blind transfers. 407 * * If the SCSI controller finishes sending/receiving data before we do, 408 * the same general logic IC will generate a /BERR for us in short order. 409 * * The fault address for said /BERR minus the base address for the 410 * transfer will be the amount of data that was actually written. 411 * 412 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 413 * detect and handle the bus error for early termination of a command. 414 * This is usually caused by a disconnecting target. 415 */ 416 void 417 sbc_drq_intr(void *p) 418 { 419 struct sbc_softc *sc = (struct sbc_softc *)p; 420 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 421 struct sci_req *sr = ncr_sc->sc_current; 422 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 423 label_t faultbuf; 424 volatile u_int32_t *long_drq; 425 u_int32_t *long_data; 426 volatile u_int8_t *drq = 0; /* XXX gcc4 -Wuninitialized */ 427 u_int8_t *data; 428 int count, dcount, resid; 429 u_int8_t tmp; 430 431 /* 432 * If we're not ready to xfer data, or have no more, just return. 433 */ 434 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 435 return; 436 437 #ifdef SBC_DEBUG 438 if (sbc_debug & SBC_DB_INTR) 439 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 440 device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags); 441 #endif 442 443 /* 444 * Setup for a possible bus error caused by SCSI controller 445 * switching out of DATA-IN/OUT before we're done with the 446 * current transfer. 447 */ 448 nofault = &faultbuf; 449 450 if (setjmp(nofault)) { 451 nofault = (label_t *)0; 452 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 453 count = (( (u_long)m68k_fault_addr 454 - (u_long)sc->sc_drq_addr)); 455 456 if ((count < 0) || (count > dh->dh_len)) { 457 printf("%s: complete=0x%x (pending 0x%x)\n", 458 device_xname(ncr_sc->sc_dev), count, 459 dh->dh_len); 460 panic("something is wrong"); 461 } 462 463 dh->dh_addr += count; 464 dh->dh_len -= count; 465 } else 466 count = 0; 467 468 #ifdef SBC_DEBUG 469 if (sbc_debug & SBC_DB_INTR) 470 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 471 device_xname(ncr_sc->sc_dev), count, dh->dh_len); 472 #endif 473 m68k_fault_addr = 0; 474 475 return; 476 } 477 478 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 479 dcount = 0; 480 481 /* 482 * Get the source address aligned. 483 */ 484 resid = 485 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 486 if (count && count < 4) { 487 drq = (volatile u_int8_t *)sc->sc_drq_addr; 488 data = (u_int8_t *)dh->dh_addr; 489 490 #define W1 *drq++ = *data++ 491 while (count) { 492 W1; count--; 493 } 494 #undef W1 495 dh->dh_addr += resid; 496 dh->dh_len -= resid; 497 } 498 499 /* 500 * Start the transfer. 501 */ 502 while (dh->dh_len) { 503 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 504 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 505 long_data = (u_int32_t *)dh->dh_addr; 506 507 #define W4 *long_drq++ = *long_data++ 508 while (count >= 64) { 509 W4; W4; W4; W4; W4; W4; W4; W4; 510 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 511 count -= 64; 512 } 513 while (count >= 4) { 514 W4; count -= 4; 515 } 516 #undef W4 517 data = (u_int8_t *)long_data; 518 drq = (volatile u_int8_t *)long_drq; 519 520 #define W1 *drq++ = *data++ 521 while (count) { 522 W1; count--; 523 } 524 #undef W1 525 dh->dh_len -= dcount; 526 dh->dh_addr += dcount; 527 } 528 dh->dh_flags |= SBC_DH_DONE; 529 530 /* 531 * XXX -- Read a byte from the SBC to trigger a /BERR. 532 * This seems to be necessary for us to notice that 533 * the target has disconnected. Ick. 06 jun 1996 (sr) 534 */ 535 if (dcount >= MAX_DMA_LEN) 536 drq = (volatile u_int8_t *)sc->sc_drq_addr; 537 tmp = *drq; 538 } else { /* Data In */ 539 /* 540 * Get the dest address aligned. 541 */ 542 resid = 543 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 544 if (count && count < 4) { 545 data = (u_int8_t *)dh->dh_addr; 546 drq = (volatile u_int8_t *)sc->sc_drq_addr; 547 while (count) { 548 *data++ = *drq++; 549 count--; 550 } 551 dh->dh_addr += resid; 552 dh->dh_len -= resid; 553 } 554 555 /* 556 * Start the transfer. 557 */ 558 while (dh->dh_len) { 559 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 560 long_data = (u_int32_t *)dh->dh_addr; 561 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 562 563 #define R4 *long_data++ = *long_drq++ 564 while (count >= 64) { 565 R4; R4; R4; R4; R4; R4; R4; R4; 566 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 567 count -= 64; 568 } 569 while (count >= 4) { 570 R4; count -= 4; 571 } 572 #undef R4 573 data = (u_int8_t *)long_data; 574 drq = (volatile u_int8_t *)long_drq; 575 while (count) { 576 *data++ = *drq++; 577 count--; 578 } 579 dh->dh_len -= dcount; 580 dh->dh_addr += dcount; 581 } 582 dh->dh_flags |= SBC_DH_DONE; 583 } 584 585 /* 586 * OK. No bus error occurred above. Clear the nofault flag 587 * so we no longer short-circuit bus errors. 588 */ 589 nofault = (label_t *)0; 590 591 #ifdef SBC_DEBUG 592 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 593 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 594 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 595 *ncr_sc->sci_bus_csr); 596 #endif 597 } 598 599 void 600 sbc_dma_alloc(struct ncr5380_softc *ncr_sc) 601 { 602 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 603 struct sci_req *sr = ncr_sc->sc_current; 604 struct scsipi_xfer *xs = sr->sr_xs; 605 struct sbc_pdma_handle *dh; 606 int i, xlen; 607 608 #ifdef DIAGNOSTIC 609 if (sr->sr_dma_hand != NULL) 610 panic("sbc_dma_alloc: already have PDMA handle"); 611 #endif 612 613 /* Polled transfers shouldn't allocate a PDMA handle. */ 614 if (sr->sr_flags & SR_IMMED) 615 return; 616 617 xlen = ncr_sc->sc_datalen; 618 619 /* Make sure our caller checked sc_min_dma_len. */ 620 if (xlen < MIN_DMA_LEN) 621 panic("sbc_dma_alloc: len=0x%x", xlen); 622 623 /* 624 * Find free PDMA handle. Guaranteed to find one since we 625 * have as many PDMA handles as the driver has processes. 626 * (instances?) 627 */ 628 for (i = 0; i < SCI_OPENINGS; i++) { 629 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 630 goto found; 631 } 632 panic("sbc: no free PDMA handles"); 633 found: 634 dh = &sc->sc_pdma[i]; 635 dh->dh_flags = SBC_DH_BUSY; 636 dh->dh_addr = ncr_sc->sc_dataptr; 637 dh->dh_len = xlen; 638 639 /* Copy the 'write' flag for convenience. */ 640 if (xs->xs_control & XS_CTL_DATA_OUT) 641 dh->dh_flags |= SBC_DH_OUT; 642 643 sr->sr_dma_hand = dh; 644 } 645 646 void 647 sbc_dma_free(struct ncr5380_softc *ncr_sc) 648 { 649 struct sci_req *sr = ncr_sc->sc_current; 650 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 651 652 #ifdef DIAGNOSTIC 653 if (sr->sr_dma_hand == NULL) 654 panic("sbc_dma_free: no DMA handle"); 655 #endif 656 657 if (ncr_sc->sc_state & NCR_DOINGDMA) 658 panic("sbc_dma_free: free while in progress"); 659 660 if (dh->dh_flags & SBC_DH_BUSY) { 661 dh->dh_flags = 0; 662 dh->dh_addr = NULL; 663 dh->dh_len = 0; 664 } 665 sr->sr_dma_hand = NULL; 666 } 667 668 void 669 sbc_dma_poll(struct ncr5380_softc *ncr_sc) 670 { 671 struct sci_req *sr = ncr_sc->sc_current; 672 673 /* 674 * We shouldn't arrive here; if SR_IMMED is set, then 675 * dma_alloc() should have refused to allocate a handle 676 * for the transfer. This forces the polled PDMA code 677 * to handle the request... 678 */ 679 #ifdef SBC_DEBUG 680 if (sbc_debug & SBC_DB_DMA) 681 printf("%s: lost DRQ interrupt?\n", 682 device_xname(ncr_sc->sc_dev)); 683 #endif 684 sr->sr_flags |= SR_OVERDUE; 685 } 686 687 void 688 sbc_dma_setup(struct ncr5380_softc *ncr_sc) 689 { 690 /* Not needed; we don't have real DMA */ 691 } 692 693 void 694 sbc_dma_start(struct ncr5380_softc *ncr_sc) 695 { 696 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 697 struct sci_req *sr = ncr_sc->sc_current; 698 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 699 700 /* 701 * Match bus phase, clear pending interrupts, set DMA mode, and 702 * assert data bus (for writing only), then start the transfer. 703 */ 704 if (dh->dh_flags & SBC_DH_OUT) { 705 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 706 SCI_CLR_INTR(ncr_sc); 707 if (sc->sc_clrintr) 708 (*sc->sc_clrintr)(ncr_sc); 709 *ncr_sc->sci_mode |= SCI_MODE_DMA; 710 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 711 *ncr_sc->sci_dma_send = 0; 712 } else { 713 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 714 SCI_CLR_INTR(ncr_sc); 715 if (sc->sc_clrintr) 716 (*sc->sc_clrintr)(ncr_sc); 717 *ncr_sc->sci_mode |= SCI_MODE_DMA; 718 *ncr_sc->sci_icmd = 0; 719 *ncr_sc->sci_irecv = 0; 720 } 721 ncr_sc->sc_state |= NCR_DOINGDMA; 722 723 #ifdef SBC_DEBUG 724 if (sbc_debug & SBC_DB_DMA) 725 printf("%s: PDMA started, va=%p, len=0x%x\n", 726 device_xname(ncr_sc->sc_dev), dh->dh_addr, dh->dh_len); 727 #endif 728 } 729 730 void 731 sbc_dma_eop(struct ncr5380_softc *ncr_sc) 732 { 733 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 734 } 735 736 void 737 sbc_dma_stop(struct ncr5380_softc *ncr_sc) 738 { 739 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 740 struct sci_req *sr = ncr_sc->sc_current; 741 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 742 int ntrans; 743 744 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 745 #ifdef SBC_DEBUG 746 if (sbc_debug & SBC_DB_DMA) 747 printf("%s: dma_stop: DMA not running\n", 748 device_xname(ncr_sc->sc_dev)); 749 #endif 750 return; 751 } 752 ncr_sc->sc_state &= ~NCR_DOINGDMA; 753 754 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 755 ntrans = ncr_sc->sc_datalen - dh->dh_len; 756 757 #ifdef SBC_DEBUG 758 if (sbc_debug & SBC_DB_DMA) 759 printf("%s: dma_stop: ntrans=0x%x\n", 760 device_xname(ncr_sc->sc_dev), ntrans); 761 #endif 762 763 if (ntrans > ncr_sc->sc_datalen) 764 panic("sbc_dma_stop: excess transfer"); 765 766 /* Adjust data pointer */ 767 ncr_sc->sc_dataptr += ntrans; 768 ncr_sc->sc_datalen -= ntrans; 769 770 /* Clear any pending interrupts. */ 771 SCI_CLR_INTR(ncr_sc); 772 if (sc->sc_clrintr) 773 (*sc->sc_clrintr)(ncr_sc); 774 } 775 776 /* Put SBIC back into PIO mode. */ 777 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 778 *ncr_sc->sci_icmd = 0; 779 780 #ifdef SBC_DEBUG 781 if (sbc_debug & SBC_DB_REG) 782 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 783 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 784 *ncr_sc->sci_bus_csr); 785 #endif 786 } 787