1 /* $NetBSD: mac68k5380.c,v 1.30 1997/04/15 03:22:50 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Allen Briggs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Allen Briggs 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Derived from atari5380.c for the mac68k port of NetBSD. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/dkstat.h> 41 #include <sys/syslog.h> 42 #include <sys/buf.h> 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsi_message.h> 45 #include <scsi/scsiconf.h> 46 47 /* 48 * Include the driver definitions 49 */ 50 #include "ncr5380reg.h" 51 52 #include <machine/stdarg.h> 53 #include <machine/viareg.h> 54 55 #include "ncr5380var.h" 56 57 /* 58 * Set the various driver options 59 */ 60 #define NREQ 18 /* Size of issue queue */ 61 #define AUTO_SENSE 1 /* Automatically issue a request-sense */ 62 63 #define DRNAME ncrscsi /* used in various prints */ 64 #undef DBG_SEL /* Show the selection process */ 65 #undef DBG_REQ /* Show enqueued/ready requests */ 66 #undef DBG_NOWRITE /* Do not allow writes to the targets */ 67 #undef DBG_PIO /* Show the polled-I/O process */ 68 #undef DBG_INF /* Show information transfer process */ 69 #define DBG_NOSTATIC /* No static functions, all in DDB trace*/ 70 #define DBG_PID 25 /* Keep track of driver */ 71 #ifdef DBG_NOSTATIC 72 # define static 73 #endif 74 #ifdef DBG_SEL 75 # define DBG_SELPRINT(a,b) printf(a,b) 76 #else 77 # define DBG_SELPRINT(a,b) 78 #endif 79 #ifdef DBG_PIO 80 # define DBG_PIOPRINT(a,b,c) printf(a,b,c) 81 #else 82 # define DBG_PIOPRINT(a,b,c) 83 #endif 84 #ifdef DBG_INF 85 # define DBG_INFPRINT(a,b,c) a(b,c) 86 #else 87 # define DBG_INFPRINT(a,b,c) 88 #endif 89 #ifdef DBG_PID 90 /* static char *last_hit = NULL, *olast_hit = NULL; */ 91 static char *last_hit[DBG_PID]; 92 # define PID(a) \ 93 { int i; \ 94 for (i=0; i< DBG_PID-1; i++) \ 95 last_hit[i] = last_hit[i+1]; \ 96 last_hit[DBG_PID-1] = a; } 97 #else 98 # define PID(a) 99 #endif 100 101 #undef REAL_DMA /* Use DMA if sensible */ 102 #define scsi_ipending() (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) 103 #define fair_to_keep_dma() 1 104 #define claimed_dma() 1 105 #define reconsider_dma() 106 #define USE_PDMA 1 /* Use special pdma-transfer function */ 107 #define MIN_PHYS 0x2000 /* pdma space w/ /DSACK is only 0x2000 */ 108 109 #define ENABLE_NCR5380(sc) cur_softc = sc; 110 111 /* 112 * softc of currently active controller (well, we only have one for now). 113 */ 114 115 static struct ncr_softc *cur_softc; 116 117 struct scsi_5380 { 118 volatile u_char scsi_5380[8*16]; /* 8 regs, 1 every 16th byte. */ 119 }; 120 121 extern vm_offset_t SCSIBase; 122 static volatile u_char *ncr = (volatile u_char *) 0x10000; 123 static volatile u_char *ncr_5380_with_drq = (volatile u_char *) 0x6000; 124 static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000; 125 126 #define SCSI_5380 ((struct scsi_5380 *) ncr) 127 #define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)] 128 #define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val)) 129 130 static void ncr5380_irq_intr(void *); 131 static void ncr5380_drq_intr(void *); 132 static void do_ncr5380_drq_intr __P((void *)); 133 134 static __inline__ void scsi_clr_ipend __P((void)); 135 static void scsi_mach_init __P((struct ncr_softc *sc)); 136 static int machine_match __P((struct device *parent, 137 struct cfdata *cf, void *aux, 138 struct cfdriver *cd)); 139 static __inline__ int pdma_ready __P((void)); 140 static int transfer_pdma __P((u_char *phasep, u_char *data, 141 u_long *count)); 142 143 static __inline__ void 144 scsi_clr_ipend() 145 { 146 int tmp; 147 148 tmp = GET_5380_REG(NCR5380_IRCV); 149 scsi_clear_irq(); 150 } 151 152 static void 153 scsi_mach_init(sc) 154 struct ncr_softc *sc; 155 { 156 static int initted = 0; 157 158 if (initted++) 159 panic("scsi_mach_init called again.\n"); 160 161 ncr = (volatile u_char *) 162 (SCSIBase + (u_long) ncr); 163 ncr_5380_with_drq = (volatile u_char *) 164 (SCSIBase + (u_int) ncr_5380_with_drq); 165 ncr_5380_without_drq = (volatile u_char *) 166 (SCSIBase + (u_int) ncr_5380_without_drq); 167 168 if (VIA2 == VIA2OFF) { 169 scsi_enable = Via1Base + VIA2 * 0x2000 + vIER; 170 scsi_flag = Via1Base + VIA2 * 0x2000 + vIFR; 171 } else { 172 scsi_enable = Via1Base + VIA2 * 0x2000 + rIER; 173 scsi_flag = Via1Base + VIA2 * 0x2000 + rIFR; 174 } 175 176 via2_register_irq(VIA2_SCSIIRQ, ncr5380_irq_intr, sc); 177 via2_register_irq(VIA2_SCSIDRQ, ncr5380_drq_intr, sc); 178 } 179 180 static int 181 machine_match(parent, cf, aux, cd) 182 struct device *parent; 183 struct cfdata *cf; 184 void *aux; 185 struct cfdriver *cd; 186 { 187 if (!mac68k_machine.scsi80) 188 return 0; 189 return 1; 190 } 191 192 #if USE_PDMA 193 int pdma_5380_dir = 0; 194 195 u_char *pending_5380_data; 196 u_long pending_5380_count; 197 198 #define NCR5380_PDMA_DEBUG 1 /* Maybe we try with this off eventually. */ 199 200 #if NCR5380_PDMA_DEBUG 201 int pdma_5380_sends = 0; 202 int pdma_5380_bytes = 0; 203 204 void 205 pdma_stat() 206 { 207 printf("PDMA SCSI: %d xfers completed for %d bytes.\n", 208 pdma_5380_sends, pdma_5380_bytes); 209 printf("pdma_5380_dir = %d\t", 210 pdma_5380_dir); 211 printf("datap = %p, remainder = %ld.\n", 212 pending_5380_data, pending_5380_count); 213 scsi_show(); 214 } 215 #endif 216 217 void 218 pdma_cleanup(void) 219 { 220 SC_REQ *reqp = connected; 221 int s; 222 223 s = splbio(); 224 PID("pdma_cleanup0"); 225 226 pdma_5380_dir = 0; 227 228 #if NCR5380_PDMA_DEBUG 229 pdma_5380_sends++; 230 pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count); 231 #endif 232 233 /* 234 * Update pointers. 235 */ 236 reqp->xdata_ptr += reqp->xdata_len - pending_5380_count; 237 reqp->xdata_len = pending_5380_count; 238 239 /* 240 * Reset DMA mode. 241 */ 242 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 243 244 /* 245 * Clear any pending interrupts. 246 */ 247 scsi_clr_ipend(); 248 249 /* 250 * Tell interrupt functions that DMA has ended. 251 */ 252 reqp->dr_flag &= ~DRIVER_IN_DMA; 253 254 SET_5380_REG(NCR5380_MODE, IMODE_BASE); 255 SET_5380_REG(NCR5380_ICOM, 0); 256 257 splx(s); 258 259 /* 260 * Back for more punishment. 261 */ 262 PID("pdma_cleanup1"); 263 run_main(cur_softc); 264 PID("pdma_cleanup2"); 265 } 266 #endif 267 268 static __inline__ int 269 pdma_ready() 270 { 271 #if USE_PDMA 272 SC_REQ *reqp = connected; 273 int dmstat, idstat; 274 extern u_char ncr5380_no_parchk; 275 276 PID("pdma_ready0"); 277 if (pdma_5380_dir) { 278 PID("pdma_ready1."); 279 /* 280 * For a phase mis-match, ATN is a "don't care," IRQ is 1 and 281 * all other bits in the Bus & Status Register are 0. Also, 282 * the current SCSI Bus Status Register has a 1 for BSY and 283 * REQ. Since we're just checking that this interrupt isn't a 284 * reselection or a reset, we just check for either. 285 */ 286 dmstat = GET_5380_REG(NCR5380_DMSTAT); 287 idstat = GET_5380_REG(NCR5380_IDSTAT); 288 if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET) 289 && ((idstat & (SC_S_BSY|SC_S_REQ)) 290 == (SC_S_BSY | SC_S_REQ)) ) { 291 PID("pdma_ready2"); 292 pdma_cleanup(); 293 return 1; 294 } else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) { 295 if (!(ncr5380_no_parchk & (1 << reqp->targ_id))) 296 /* XXX: Should be parity error ???? */ 297 reqp->xs->error = XS_DRIVER_STUFFUP; 298 PID("pdma_ready3"); 299 /* XXX: is this the right reaction? */ 300 pdma_cleanup(); 301 return 1; 302 } else if ( !(idstat & SC_S_REQ) 303 || (((idstat>>2) & 7) != reqp->phase)) { 304 #ifdef DIAGNOSTIC 305 /* XXX: is this the right reaction? Can this happen? */ 306 scsi_show(); 307 printf("Unexpected phase change.\n"); 308 #endif 309 reqp->xs->error = XS_DRIVER_STUFFUP; 310 pdma_cleanup(); 311 return 1; 312 } else { 313 scsi_show(); 314 panic("Spurious interrupt during PDMA xfer.\n"); 315 } 316 } else 317 PID("pdma_ready4"); 318 #endif 319 return 0; 320 } 321 322 static void 323 ncr5380_irq_intr(p) 324 void *p; 325 { 326 PID("irq"); 327 328 #if USE_PDMA 329 if (pdma_ready()) { 330 return; 331 } 332 #endif 333 scsi_idisable(); 334 ncr_ctrl_intr(cur_softc); 335 } 336 337 /* 338 * This is the meat of the PDMA transfer. 339 * When we get here, we shove data as fast as the mac can take it. 340 * We depend on several things: 341 * * All macs after the Mac Plus that have a 5380 chip should have a general 342 * logic IC that handshakes data for blind transfers. 343 * * If the SCSI controller finishes sending/receiving data before we do, 344 * the same general logic IC will generate a /BERR for us in short order. 345 * * The fault address for said /BERR minus the base address for the 346 * transfer will be the amount of data that was actually written. 347 * 348 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 349 * detect and handle the bus error for early termination of a command. 350 * This is usually caused by a disconnecting target. 351 */ 352 static void 353 do_ncr5380_drq_intr(p) 354 void *p; 355 { 356 #if USE_PDMA 357 extern int *nofault, mac68k_buserr_addr; 358 label_t faultbuf; 359 register int count; 360 volatile u_int32_t *long_drq; 361 u_int32_t *long_data; 362 volatile u_int8_t *drq, tmp_data; 363 u_int8_t *data; 364 365 #if DBG_PID 366 if (pdma_5380_dir == 2) { 367 PID("drq (in)"); 368 } else { 369 PID("drq (out)"); 370 } 371 #endif 372 373 /* 374 * Setup for a possible bus error caused by SCSI controller 375 * switching out of DATA-IN/OUT before we're done with the 376 * current transfer. 377 */ 378 nofault = (int *) &faultbuf; 379 380 if (setjmp((label_t *) nofault)) { 381 PID("drq berr"); 382 nofault = (int *) 0; 383 count = ( (u_long) mac68k_buserr_addr 384 - (u_long) ncr_5380_with_drq); 385 if ((count < 0) || (count > pending_5380_count)) { 386 printf("pdma %s: cnt = %d (0x%x) (pending cnt %ld)\n", 387 (pdma_5380_dir == 2) ? "in" : "out", 388 count, count, pending_5380_count); 389 panic("something is wrong"); 390 } 391 392 pending_5380_data += count; 393 pending_5380_count -= count; 394 395 mac68k_buserr_addr = 0; 396 397 PID("end drq early"); 398 399 return; 400 } 401 402 if (pdma_5380_dir == 2) { /* Data In */ 403 int resid; 404 405 /* 406 * Get the dest address aligned. 407 */ 408 resid = count = min(pending_5380_count, 409 4 - (((int) pending_5380_data) & 0x3)); 410 if (count && (count < 4)) { 411 data = (u_int8_t *) pending_5380_data; 412 drq = (u_int8_t *) ncr_5380_with_drq; 413 while (count) { 414 #define R1 *data++ = *drq++ 415 R1; count--; 416 #undef R1 417 } 418 pending_5380_data += resid; 419 pending_5380_count -= resid; 420 } 421 422 /* 423 * Get ready to start the transfer. 424 */ 425 while (pending_5380_count) { 426 int dcount; 427 428 dcount = count = min(pending_5380_count, MIN_PHYS); 429 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 430 long_data = (u_int32_t *) pending_5380_data; 431 432 #define R4 *long_data++ = *long_drq++ 433 while ( count > 64 ) { 434 R4; R4; R4; R4; R4; R4; R4; R4; 435 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 436 count -= 64; 437 } 438 while (count > 8) { 439 R4; R4; count -= 8; 440 } 441 #undef R4 442 data = (u_int8_t *) long_data; 443 drq = (u_int8_t *) long_drq; 444 while (count) { 445 #define R1 *data++ = *drq++ 446 R1; count--; 447 #undef R1 448 } 449 pending_5380_count -= dcount; 450 pending_5380_data += dcount; 451 } 452 /* 453 * OK. No bus error occurred above. Clear the nofault flag 454 * so we no longer short-circuit bus errors. 455 */ 456 nofault = (int *) 0; 457 458 } else { 459 int resid; 460 461 /* 462 * Get the source address aligned. 463 */ 464 resid = count = min(pending_5380_count, 465 4 - (((int) pending_5380_data) & 0x3)); 466 if (count && (count < 4)) { 467 data = (u_int8_t *) pending_5380_data; 468 drq = (u_int8_t *) ncr_5380_with_drq; 469 while (count) { 470 #define W1 *drq++ = *data++ 471 W1; count--; 472 #undef W1 473 } 474 pending_5380_data += resid; 475 pending_5380_count -= resid; 476 } 477 478 /* 479 * Get ready to start the transfer. 480 */ 481 while (pending_5380_count) { 482 int dcount; 483 484 dcount = count = min(pending_5380_count, MIN_PHYS); 485 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 486 long_data = (u_int32_t *) pending_5380_data; 487 488 #define W4 *long_drq++ = *long_data++ 489 while ( count > 64 ) { 490 W4; W4; W4; W4; W4; W4; W4; W4; 491 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 492 count -= 64; 493 } 494 while ( count > 8 ) { 495 W4; W4; 496 count -= 8; 497 } 498 #undef W4 499 data = (u_int8_t *) long_data; 500 drq = (u_int8_t *) long_drq; 501 while (count) { 502 #define W1 *drq++ = *data++ 503 W1; count--; 504 #undef W1 505 } 506 pending_5380_count -= dcount; 507 pending_5380_data += dcount; 508 } 509 510 PID("write complete"); 511 512 /* 513 * OK. No bus error occurred above. Clear the nofault flag 514 * so we no longer short-circuit bus errors. 515 */ 516 nofault = (int *) 0; 517 518 drq = (volatile u_int8_t *) ncr_5380_with_drq; 519 tmp_data = *drq; 520 521 PID("read a byte to force a phase change"); 522 } 523 524 PID("end drq"); 525 return; 526 #else 527 return; 528 #endif /* if USE_PDMA */ 529 } 530 531 static void 532 ncr5380_drq_intr(p) 533 void *p; 534 { 535 while (GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ) { 536 do_ncr5380_drq_intr(p); 537 scsi_clear_drq(); 538 } 539 } 540 541 #if USE_PDMA 542 543 #define SCSI_TIMEOUT_VAL 10000000 544 545 static int 546 transfer_pdma(phasep, data, count) 547 u_char *phasep; 548 u_char *data; 549 u_long *count; 550 { 551 SC_REQ *reqp = connected; 552 int len = *count, s, scsi_timeout = SCSI_TIMEOUT_VAL; 553 554 if (pdma_5380_dir) { 555 panic("ncrscsi: transfer_pdma called when operation already " 556 "pending.\n"); 557 } 558 PID("transfer_pdma0") 559 560 /* 561 * Don't bother with PDMA if we can't sleep or for small transfers. 562 */ 563 if (reqp->dr_flag & DRIVER_NOINT) { 564 PID("pdma, falling back to transfer_pio.") 565 transfer_pio(phasep, data, count, 0); 566 return -1; 567 } 568 569 /* 570 * We are probably already at spl2(), so this is likely a no-op. 571 * Paranoia. 572 */ 573 s = splbio(); 574 575 scsi_idisable(); 576 577 /* 578 * Match phases with target. 579 */ 580 SET_5380_REG(NCR5380_TCOM, *phasep); 581 582 /* 583 * Clear pending interrupts. 584 */ 585 scsi_clr_ipend(); 586 587 /* 588 * Wait until target asserts BSY. 589 */ 590 while ( ((GET_5380_REG(NCR5380_IDSTAT) & SC_S_BSY) == 0) 591 && (--scsi_timeout) ); 592 if (!scsi_timeout) { 593 #if DIAGNOSTIC 594 printf("scsi timeout: waiting for BSY in %s.\n", 595 (*phasep == PH_DATAOUT) ? "pdma_out" : "pdma_in"); 596 #endif 597 goto scsi_timeout_error; 598 } 599 600 /* 601 * Tell the driver that we're in DMA mode. 602 */ 603 reqp->dr_flag |= DRIVER_IN_DMA; 604 605 /* 606 * Load transfer values for DRQ interrupt handlers. 607 */ 608 pending_5380_data = data; 609 pending_5380_count = len; 610 611 /* 612 * Set the transfer function to be called on DRQ interrupts. 613 * And note that we're waiting. 614 */ 615 switch (*phasep) { 616 default: 617 panic("Unexpected phase in transfer_pdma.\n"); 618 case PH_DATAOUT: 619 pdma_5380_dir = 1; 620 SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM)|SC_ADTB); 621 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 622 SET_5380_REG(NCR5380_DMSTAT, 0); 623 break; 624 case PH_DATAIN: 625 pdma_5380_dir = 2; 626 SET_5380_REG(NCR5380_ICOM, 0); 627 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 628 SET_5380_REG(NCR5380_IRCV, 0); 629 break; 630 } 631 632 PID("waiting for interrupt.") 633 634 /* 635 * Now that we're set up, enable interrupts and drop processor 636 * priority back down. 637 */ 638 scsi_ienable(); 639 splx(s); 640 return 0; 641 642 scsi_timeout_error: 643 /* 644 * Clear the DMA mode. 645 */ 646 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 647 return -1; 648 } 649 #endif /* if USE_PDMA */ 650 651 /* Include general routines. */ 652 #include <mac68k/dev/ncr5380.c> 653