1 /* $NetBSD: if_aereg.h,v 1.5 1994/12/04 19:40:16 briggs Exp $ */ 2 3 /* 4 * National Semiconductor DS8390 NIC register definitions 5 * 6 * $Id: if_aereg.h,v 1.5 1994/12/04 19:40:16 briggs Exp $ 7 * 8 */ 9 10 /* 11 * Page 0 register offsets 12 */ 13 #define AE_P0_CR 0x00 /* Command Register */ 14 15 #define AE_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 16 #define AE_P0_PSTART 0x01 /* Page Start register (write) */ 17 18 #define AE_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 19 #define AE_P0_PSTOP 0x02 /* Page Stop register (write) */ 20 21 #define AE_P0_BNRY 0x03 /* Boundary Pointer */ 22 23 #define AE_P0_TSR 0x04 /* Transmit Status Register (read) */ 24 #define AE_P0_TPSR 0x04 /* Transmit Page Start (write) */ 25 26 #define AE_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 27 #define AE_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 28 29 #define AE_P0_FIFO 0x06 /* FIFO register (read) */ 30 #define AE_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 31 32 #define AE_P0_ISR 0x07 /* Interrupt Status Register */ 33 34 #define AE_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 35 #define AE_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 36 37 #define AE_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 38 #define AE_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 39 40 #define AE_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 41 42 #define AE_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 43 44 #define AE_P0_RSR 0x0c /* Receive Status (read) */ 45 #define AE_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 46 47 #define AE_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 48 #define AE_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 49 50 #define AE_P0_CNTR1 0x0e /* CRC error counter (read) */ 51 #define AE_P0_DCR 0x0e /* Data Configuration Reg (write) */ 52 53 #define AE_P0_CNTR2 0x0f /* missed packet counter (read) */ 54 #define AE_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 55 56 /* 57 * Page 1 register offsets 58 */ 59 #define AE_P1_CR 0x00 /* Command Register */ 60 #define AE_P1_PAR0 0x01 /* Physical Address Register 0 */ 61 #define AE_P1_PAR1 0x02 /* Physical Address Register 1 */ 62 #define AE_P1_PAR2 0x03 /* Physical Address Register 2 */ 63 #define AE_P1_PAR3 0x04 /* Physical Address Register 3 */ 64 #define AE_P1_PAR4 0x05 /* Physical Address Register 4 */ 65 #define AE_P1_PAR5 0x06 /* Physical Address Register 5 */ 66 #define AE_P1_CURR 0x07 /* Current RX ring-buffer page */ 67 #define AE_P1_MAR0 0x08 /* Multicast Address Register 0 */ 68 #define AE_P1_MAR1 0x09 /* Multicast Address Register 1 */ 69 #define AE_P1_MAR2 0x0a /* Multicast Address Register 2 */ 70 #define AE_P1_MAR3 0x0b /* Multicast Address Register 3 */ 71 #define AE_P1_MAR4 0x0c /* Multicast Address Register 4 */ 72 #define AE_P1_MAR5 0x0d /* Multicast Address Register 5 */ 73 #define AE_P1_MAR6 0x0e /* Multicast Address Register 6 */ 74 #define AE_P1_MAR7 0x0f /* Multicast Address Register 7 */ 75 76 /* 77 * Page 2 register offsets 78 */ 79 #define AE_P2_CR 0x00 /* Command Register */ 80 #define AE_P2_PSTART 0x01 /* Page Start (read) */ 81 #define AE_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 82 #define AE_P2_PSTOP 0x02 /* Page Stop (read) */ 83 #define AE_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 84 #define AE_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 85 #define AE_P2_TPSR 0x04 /* Transmit Page Start (read) */ 86 #define AE_P2_LNPP 0x05 /* Local Next Packet Pointer */ 87 #define AE_P2_ACU 0x06 /* Address Counter Upper */ 88 #define AE_P2_ACL 0x07 /* Address Counter Lower */ 89 #define AE_P2_RCR 0x0c /* Receive Configuration Register (read) */ 90 #define AE_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 91 #define AE_P2_DCR 0x0e /* Data Configuration Register (read) */ 92 #define AE_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 93 94 /* 95 * Command Register (CR) definitions 96 */ 97 98 /* 99 * STP: SToP. Software reset command. Takes the controller offline. No 100 * packets will be received or transmitted. Any reception or 101 * transmission in progress will continue to completion before 102 * entering reset state. To exit this state, the STP bit must 103 * reset and the STA bit must be set. The software reset has 104 * executed only when indicated by the RST bit in the ISR being 105 * set. 106 */ 107 #define AE_CR_STP 0x01 108 109 /* 110 * STA: STArt. This bit is used to activate the NIC after either power-up, 111 * or when the NIC has been put in reset mode by software command 112 * or error. 113 */ 114 #define AE_CR_STA 0x02 115 116 /* 117 * TXP: Transmit Packet. This bit must be set to indicate transmission of 118 * a packet. TXP is internally reset either after the transmission is 119 * completed or aborted. This bit should be set only after the Transmit 120 * Byte Count and Transmit Page Start register have been programmed. 121 */ 122 #define AE_CR_TXP 0x04 123 124 /* 125 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 126 * of the remote DMA channel. RD2 can be set to abort any remote DMA 127 * command in progress. The Remote Byte Count registers should be cleared 128 * when a remote DMA has been aborted. The Remote Start Addresses are not 129 * restored to the starting address if the remote DMA is aborted. 130 * 131 * RD2 RD1 RD0 function 132 * 0 0 0 not allowed 133 * 0 0 1 remote read 134 * 0 1 0 remote write 135 * 0 1 1 send packet 136 * 1 X X abort 137 */ 138 #define AE_CR_RD0 0x08 139 #define AE_CR_RD1 0x10 140 #define AE_CR_RD2 0x20 141 142 /* 143 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 144 * access. 145 * 146 * PS1 PS0 page 147 * 0 0 0 148 * 0 1 1 149 * 1 0 2 150 * 1 1 reserved 151 */ 152 #define AE_CR_PS0 0x40 153 #define AE_CR_PS1 0x80 154 /* bit encoded aliases */ 155 #define AE_CR_PAGE_0 0x00 /* (for consistency) */ 156 #define AE_CR_PAGE_1 0x40 157 #define AE_CR_PAGE_2 0x80 158 159 /* 160 * Interrupt Status Register (ISR) definitions 161 */ 162 163 /* 164 * PRX: Packet Received. Indicates packet received with no errors. 165 */ 166 #define AE_ISR_PRX 0x01 167 168 /* 169 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 170 */ 171 #define AE_ISR_PTX 0x02 172 173 /* 174 * RXE: Receive Error. Indicates that a packet was received with one or more 175 * the following errors: CRC error, frame alignment error, FIFO overrun, 176 * missed packet. 177 */ 178 #define AE_ISR_RXE 0x04 179 180 /* 181 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 182 * resulted in one or more of the following errors: excessive 183 * collisions, FIFO underrun. 184 */ 185 #define AE_ISR_TXE 0x08 186 187 /* 188 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 189 * would exceed (has exceeded?) the boundry pointer, resulting in data 190 * that was previously received and not yet read from the buffer to be 191 * overwritten. 192 */ 193 #define AE_ISR_OVW 0x10 194 195 /* 196 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 197 * Counters has been set. 198 */ 199 #define AE_ISR_CNT 0x20 200 201 /* 202 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 203 */ 204 #define AE_ISR_RDC 0x40 205 206 /* 207 * RST: Reset status. Set when the NIC enters the reset state and cleared when a 208 * Start Command is issued to the CR. This bit is also set when a receive 209 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 210 * packets have been removed from the ring. This is a read-only bit. 211 */ 212 #define AE_ISR_RST 0x80 213 214 /* 215 * Interrupt Mask Register (IMR) definitions 216 */ 217 218 /* 219 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 220 * an interrupt. 221 */ 222 #define AE_IMR_PRXE 0x01 223 224 /* 225 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 226 * a packet transmission completes. 227 */ 228 #define AE_IMR_PTXE 0x02 229 230 /* 231 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 232 * packet is received with an error. 233 */ 234 #define AE_IMR_RXEE 0x04 235 236 /* 237 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 238 * a transmission results in an error. 239 */ 240 #define AE_IMR_TXEE 0x08 241 242 /* 243 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 244 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 245 */ 246 #define AE_IMR_OVWE 0x10 247 248 /* 249 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 250 * the MSB of one or more of the Network Statistics counters has been set. 251 */ 252 #define AE_IMR_CNTE 0x20 253 254 /* 255 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 256 * when a remote DMA transfer has completed. 257 */ 258 #define AE_IMR_RDCE 0x40 259 260 /* 261 * bit 7 is unused/reserved 262 */ 263 264 /* 265 * Data Configuration Register (DCR) definitions 266 */ 267 268 /* 269 * WTS: Word Transfer Select. WTS establishes byte or word transfers for 270 * both remote and local DMA transfers 271 */ 272 #define AE_DCR_WTS 0x01 273 274 /* 275 * BOS: Byte Order Select. BOS sets the byte order for the host. 276 * Should be 0 for 80x86, and 1 for 68000 series processors 277 */ 278 #define AE_DCR_BOS 0x02 279 280 /* 281 * LAS: Long Address Select. When LAS is 1, the contents of the remote 282 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 283 */ 284 #define AE_DCR_LAS 0x04 285 286 #ifdef huh 287 /* 288 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 289 * of the TCR must also be programmed for loopback operation. 290 * When 1, normal operation is selected. 291 */ 292 #define AE_DCR_LS 0x08 293 #endif 294 /* 295 * BMS: Burst Mode Select 296 */ 297 #define AE_DCR_BMS 0x08 298 299 /* 300 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 301 * under program control. When 1, remote DMA is automatically initiated 302 * and the boundry pointer is automatically updated 303 */ 304 #define AE_DCR_AR 0x10 305 306 /* 307 * FT0, FT1: Fifo Threshold select. 308 * FT1 FT0 Word-width Byte-width 309 * 0 0 1 word 2 bytes 310 * 0 1 2 words 4 bytes 311 * 1 0 4 words 8 bytes 312 * 1 1 8 words 12 bytes 313 * 314 * During transmission, the FIFO threshold indicates the number of bytes 315 * or words that the FIFO has filled from the local DMA before BREQ is 316 * asserted. The transmission threshold is 16 bytes minus the receiver 317 * threshold. 318 */ 319 #define AE_DCR_FT0 0x20 320 #define AE_DCR_FT1 0x40 321 322 /* 323 * bit 7 (0x80) is unused/reserved 324 */ 325 326 /* 327 * Transmit Configuration Register (TCR) definitions 328 */ 329 330 /* 331 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 332 * is not appended by the transmitter. 333 */ 334 #define AE_TCR_CRC 0x01 335 336 /* 337 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 338 * to be performed. 339 * 340 * LB1 LB0 mode 341 * 0 0 0 - normal operation (DCR_LS = 0) 342 * 0 1 1 - internal loopback (DCR_LS = 0) 343 * 1 0 2 - external loopback (DCR_LS = 1) 344 * 1 1 3 - external loopback (DCR_LS = 0) 345 */ 346 #define AE_TCR_LB0 0x02 347 #define AE_TCR_LB1 0x04 348 349 /* 350 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 351 * another station to disable the NIC's transmitter by transmitting to 352 * a multicast address hashing to bit 62. Reception of a multicast address 353 * hashing to bit 63 enables the transmitter. 354 */ 355 #define AE_TCR_ATD 0x08 356 357 /* 358 * OFST: Collision Offset enable. This bit when set modifies the backoff 359 * algorithm to allow prioritization of nodes. 360 */ 361 #define AE_TCR_OFST 0x10 362 363 /* 364 * bits 5, 6, and 7 are unused/reserved 365 */ 366 367 /* 368 * Transmit Status Register (TSR) definitions 369 */ 370 371 /* 372 * PTX: Packet Transmitted. Indicates successful transmission of packet. 373 */ 374 #define AE_TSR_PTX 0x01 375 376 /* 377 * bit 1 (0x02) is unused/reserved 378 */ 379 380 /* 381 * COL: Transmit Collided. Indicates that the transmission collided at least 382 * once with another station on the network. 383 */ 384 #define AE_TSR_COL 0x04 385 386 /* 387 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 388 * excessive collisions. 389 */ 390 #define AE_TSR_ABT 0x08 391 392 /* 393 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 394 * transmission of the packet. (Transmission is not aborted because 395 * of a loss of carrier) 396 */ 397 #define AE_TSR_CRS 0x10 398 399 /* 400 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 401 * transmission memory before the FIFO emptied. Transmission of the 402 * packet was aborted. 403 */ 404 #define AE_TSR_FU 0x20 405 406 /* 407 * CDH: CD Heartbeat. Indicates that the collision detection circuitry 408 * isn't working correctly during a collision heartbeat test. 409 */ 410 #define AE_TSR_CDH 0x40 411 412 /* 413 * OWC: Out of Window Collision: Indicates that a collision occurred after 414 * a slot time (51.2us). The transmission is rescheduled just as in 415 * normal collisions. 416 */ 417 #define AE_TSR_OWC 0x80 418 419 /* 420 * Receiver Configuration Register (RCR) definitions 421 */ 422 423 /* 424 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 425 * packets with CRC and frame errors are not discarded. 426 */ 427 #define AE_RCR_SEP 0x01 428 429 /* 430 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 431 * If set to 1, packets with less than 64 byte are not discarded. 432 */ 433 #define AE_RCR_AR 0x02 434 435 /* 436 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 437 * accepted. 438 */ 439 #define AE_RCR_AB 0x04 440 441 /* 442 * AM: Accept Multicast. If set, packets sent to a multicast address are checked 443 * for a match in the hashing array. If clear, multicast packets are ignored. 444 */ 445 #define AE_RCR_AM 0x08 446 447 /* 448 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 449 * accepted. If clear, a physical destination address must match this 450 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 451 * must also be set. In addition, the multicast hashing array must be set 452 * to all 1's so that all multicast addresses are accepted. 453 */ 454 #define AE_RCR_PRO 0x10 455 456 /* 457 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 458 * but are not stored in the ring-buffer. If clear, packets are stored (normal 459 * operation). 460 */ 461 #define AE_RCR_MON 0x20 462 463 /* 464 * bits 6 and 7 are unused/reserved. 465 */ 466 467 /* 468 * Receiver Status Register (RSR) definitions 469 */ 470 471 /* 472 * PRX: Packet Received without error. 473 */ 474 #define AE_RSR_PRX 0x01 475 476 /* 477 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 478 * alignment errors. 479 */ 480 #define AE_RSR_CRC 0x02 481 482 /* 483 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 484 * a byte boundry and the CRC did not match at the last byte boundry. 485 */ 486 #define AE_RSR_FAE 0x04 487 488 /* 489 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 490 * causing it to overrun. Reception of the packet is aborted. 491 */ 492 #define AE_RSR_FO 0x08 493 494 /* 495 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 496 * the ring-buffer because of insufficient buffer space (exceeding the 497 * boundry pointer), or because the transfer to the ring-buffer was inhibited 498 * by RCR_MON - monitor mode. 499 */ 500 #define AE_RSR_MPA 0x10 501 502 /* 503 * PHY: Physical address. If 0, the packet received was sent to a physical address. 504 * If 1, the packet was accepted because of a multicast/broadcast address 505 * match. 506 */ 507 #define AE_RSR_PHY 0x20 508 509 /* 510 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 511 * mode. Cleared when the receiver exits monitor mode. 512 */ 513 #define AE_RSR_DIS 0x40 514 515 /* 516 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 517 * are active, and the transceiver has set the CD line as a result of the 518 * jabber. 519 */ 520 #define AE_RSR_DFR 0x80 521 522 /* 523 * receive ring discriptor 524 * 525 * The National Semiconductor DS8390 Network interface controller uses 526 * the following receive ring headers. The way this works is that the 527 * memory on the interface card is chopped up into 256 bytes blocks. 528 * A contiguous portion of those blocks are marked for receive packets 529 * by setting start and end block #'s in the NIC. For each packet that 530 * is put into the receive ring, one of these headers (4 bytes each) is 531 * tacked onto the front. 532 */ 533 struct ae_ring { 534 u_char rcv_status; /* received packet status */ 535 u_char next_packet; /* pointer to next packet */ 536 u_char count[2]; /* bytes in packet (length + 4) */ 537 }; 538 539 /* 540 * Common constants 541 */ 542 #define AE_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 543 #define AE_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 544 545 /* 546 * Vendor types 547 */ 548 #define AE_VENDOR_UNKNOWN 0xFF /* Unknown network card */ 549 #define AE_VENDOR_APPLE 0x00 /* Apple Ethernet card */ 550 #define AE_VENDOR_INTERLAN 0x01 /* Interlan A310 card (GatorCard) */ 551 #define AE_VENDOR_DAYNA 0x02 /* DaynaPORT E/30s (and others?) */ 552 #define AE_VENDOR_ASANTE 0x03 /* Asante MacCon II/E */ 553 554 /* 555 * Compile-time config flags 556 */ 557 /* 558 * this sets the default for enabling/disablng the tranceiver 559 */ 560 #define AE_FLAGS_DISABLE_TRANCEIVER 0x01 561 562 /* 563 * This disables the use of double transmit buffers. 564 */ 565 #define AE_FLAGS_NO_DOUBLE_BUFFERING 0x08 566 567 /* */ 568 #define GC_RESET_OFFSET 0x000c0000 /* writes here reset NIC */ 569 #define GC_ROM_OFFSET 0x000c0000 /* address prom */ 570 #define GC_DATA_OFFSET 0x000d0000 /* Offset to NIC memory */ 571 #define GC_NIC_OFFSET 0x000e0000 /* Offset to NIC registers */ 572 573 #define DP_ROM_OFFSET 0x000f0000 574 #define DP_DATA_OFFSET 0x000d0000 /* Offset to SONIC memory */ 575 #define DP_NIC_OFFSET 0x000e0000 /* Offset to SONIC registers */ 576 577 #define AE_ROM_OFFSET 0x000f0000 578 #define AE_DATA_OFFSET 0x000d0000 /* Offset to NIC memory */ 579 #define AE_NIC_OFFSET 0x000e0000 /* Offset to NIC registers */ 580