xref: /netbsd-src/sys/arch/m68k/include/pmap_motorola.h (revision b1c86f5f087524e68db12794ee9c3e3da1ab17a0)
1 /*	$NetBSD: pmap_motorola.h,v 1.30 2010/06/06 11:41:06 he Exp $	*/
2 
3 /*
4  * Copyright (c) 1991, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * the Systems Programming Group of the University of Utah Computer
9  * Science Department.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. Neither the name of the University nor the names of its contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  *	@(#)pmap.h	8.1 (Berkeley) 6/10/93
36  */
37 
38 /*
39  * Copyright (c) 1987 Carnegie-Mellon University
40  *
41  * This code is derived from software contributed to Berkeley by
42  * the Systems Programming Group of the University of Utah Computer
43  * Science Department.
44  *
45  * Redistribution and use in source and binary forms, with or without
46  * modification, are permitted provided that the following conditions
47  * are met:
48  * 1. Redistributions of source code must retain the above copyright
49  *    notice, this list of conditions and the following disclaimer.
50  * 2. Redistributions in binary form must reproduce the above copyright
51  *    notice, this list of conditions and the following disclaimer in the
52  *    documentation and/or other materials provided with the distribution.
53  * 3. All advertising materials mentioning features or use of this software
54  *    must display the following acknowledgement:
55  *	This product includes software developed by the University of
56  *	California, Berkeley and its contributors.
57  * 4. Neither the name of the University nor the names of its contributors
58  *    may be used to endorse or promote products derived from this software
59  *    without specific prior written permission.
60  *
61  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
62  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
65  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71  * SUCH DAMAGE.
72  *
73  *	@(#)pmap.h	8.1 (Berkeley) 6/10/93
74  */
75 
76 #ifndef	_M68K_PMAP_MOTOROLA_H_
77 #define	_M68K_PMAP_MOTOROLA_H_
78 
79 #ifdef _KERNEL_OPT
80 #include "opt_m68k_arch.h"
81 #endif
82 
83 #include <sys/simplelock.h>
84 #include <machine/cpu.h>
85 #include <machine/pte.h>
86 
87 /*
88  * Pmap stuff
89  */
90 struct pmap {
91 	pt_entry_t		*pm_ptab;	/* KVA of page table */
92 	st_entry_t		*pm_stab;	/* KVA of segment table */
93 	u_int			pm_stfree;	/* 040: free lev2 blocks */
94 	st_entry_t		*pm_stpa;	/* 040: ST phys addr */
95 	uint16_t		pm_sref;	/* segment table ref count */
96 	uint16_t		pm_count;	/* pmap reference count */
97 	struct simplelock	pm_lock;	/* lock on pmap */
98 	struct pmap_statistics	pm_stats;	/* pmap statistics */
99 	int			pm_ptpages;	/* more stats: PT pages */
100 };
101 
102 /*
103  * MMU specific segment values
104  *
105  * We are using following segment layout in m68k pmap_motorola.c:
106  * 68020/030 4KB/page: l1,l2,page    == 10,10,12	(%tc = 0x82c0aa00)
107  * 68020/030 8KB/page: l1,l2,page    ==  8,11,13	(%tc = 0x82d08b00)
108  * 68040/060 4KB/page: l1,l2,l3,page == 7,7,6,12	(%tc = 0x8000)
109  * 68040/060 8KB/page: l1,l2,l3,page == 7,7,5,13	(%tc = 0xc000)
110  *
111  * 68020/030 l2 size is chosen per NPTEPG, a number of page table entries
112  * per page, to use one whole page for PTEs per one segment table entry,
113  * and maybe also because 68020 HP MMU machines use simlar structures.
114  *
115  * 68040/060 layout is defined by hardware design and not configurable,
116  * as defined in <m68k/pte_motorola.h>.
117  *
118  * Even on 68040/060, we still appropriate 2-level ste-pte pmap structures
119  * for 68020/030 (derived from 4.4BSD/hp300) to handle 040's 3-level MMU.
120  * TIA_SIZE and TIB_SIZE are used to represent such pmap structures and
121  * they are also refered on 040/060.
122  *
123  * NBSEG and SEGOFSET are used to check l2 STE of the specified VA,
124  * so they have different values between 020/030 and 040/060.
125  */
126 							/*  8KB /  4KB	*/
127 #define TIB_SHIFT	(PG_SHIFT - 2)			/*   11 /   10	*/
128 #define TIB_SIZE	(1U << TIB_SHIFT)		/* 2048 / 1024	*/
129 #define TIA_SHIFT	(32 - TIB_SHIFT - PG_SHIFT)	/*    8 /   10	*/
130 #define TIA_SIZE	(1U << TIA_SHIFT)		/*  256 / 1024	*/
131 
132 #define SEGSHIFT	(TIB_SHIFT + PG_SHIFT)		/*   24 /   22	*/
133 
134 #define NBSEG30		(1U << SEGSHIFT)
135 #define NBSEG40		(1U << SG4_SHIFT2)
136 
137 #if   ( defined(M68020) ||  defined(M68030)) &&	\
138       (!defined(M68040) && !defined(M68060))
139 #define NBSEG		NBSEG30
140 #elif ( defined(M68040) ||  defined(M68060)) &&	\
141       (!defined(M68020) && !defined(M68030))
142 #define NBSEG		NBSEG40
143 #else
144 #define NBSEG		((mmutype == MMU_68040) ? NBSEG40 : NBSEG30)
145 #endif
146 
147 #define SEGOFSET	(NBSEG - 1)	/* byte offset into segment */
148 
149 #define	m68k_round_seg(x)	((((vaddr_t)(x)) + SEGOFSET) & ~SEGOFSET)
150 #define	m68k_trunc_seg(x)	((vaddr_t)(x) & ~SEGOFSET)
151 #define	m68k_seg_offset(x)	((vaddr_t)(x) & SEGOFSET)
152 
153 /*
154  * On the 040, we keep track of which level 2 blocks are already in use
155  * with the pm_stfree mask.  Bits are arranged from LSB (block 0) to MSB
156  * (block 31).  For convenience, the level 1 table is considered to be
157  * block 0.
158  *
159  * MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed
160  * for the kernel and users.
161  * 16 or 8 implies only the initial "segment table" page is used,
162  * i.e. it means PAGE_SIZE / (SG4_LEV1SIZE * sizeof(st_entry_t)).
163  * WARNING: don't change MAXUL2SIZE unless you can allocate
164  * physically contiguous pages for the ST in pmap_motorola.c!
165  */
166 #define MAXKL2SIZE	32
167 #if PAGE_SIZE == 8192	/* NBPG / (SG4_LEV1SIZE * sizeof(st_entry_t)) */
168 #define MAXUL2SIZE	16
169 #else
170 #define MAXUL2SIZE	8
171 #endif
172 #define l2tobm(n)	(1U << (n))
173 #define bmtol2(n)	(ffs(n) - 1)
174 
175 /*
176  * Macros for speed
177  */
178 #define	PMAP_ACTIVATE(pmap, loadhw)					\
179 {									\
180 	if ((loadhw))							\
181 		loadustp(m68k_btop((paddr_t)(pmap)->pm_stpa));		\
182 }
183 
184 /*
185  * For each struct vm_page, there is a list of all currently valid virtual
186  * mappings of that page.  An entry is a pv_entry, the list is pv_table.
187  */
188 struct pv_entry {
189 	struct pv_entry	*pv_next;	/* next pv_entry */
190 	struct pmap	*pv_pmap;	/* pmap where mapping lies */
191 	vaddr_t		pv_va;		/* virtual address for mapping */
192 	st_entry_t	*pv_ptste;	/* non-zero if VA maps a PT page */
193 	struct pmap	*pv_ptpmap;	/* if pv_ptste, pmap for PT page */
194 };
195 
196 struct pv_page;
197 
198 struct pv_page_info {
199 	TAILQ_ENTRY(pv_page) pgi_list;
200 	struct pv_entry *pgi_freelist;
201 	int pgi_nfree;
202 };
203 
204 /*
205  * This is basically:
206  * ((PAGE_SIZE - sizeof(struct pv_page_info)) / sizeof(struct pv_entry))
207  */
208 #if PAGE_SIZE == 8192
209 #define	NPVPPG	340
210 #else
211 #define	NPVPPG	170
212 #endif
213 
214 struct pv_page {
215 	struct pv_page_info pvp_pgi;
216 	struct pv_entry pvp_pv[NPVPPG];
217 };
218 
219 #define	active_pmap(pm) \
220 	((pm) == pmap_kernel() || (pm) == curproc->p_vmspace->vm_map.pmap)
221 #define	active_user_pmap(pm) \
222 	(curproc && \
223 	 (pm) != pmap_kernel() && (pm) == curproc->p_vmspace->vm_map.pmap)
224 
225 extern struct pv_header	*pv_table;	/* array of entries, one per page */
226 
227 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
228 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
229 
230 #define	pmap_update(pmap)		/* nothing (yet) */
231 
232 static __inline void
233 pmap_remove_all(struct pmap *pmap)
234 {
235 	/* Nothing. */
236 }
237 
238 extern paddr_t		Sysseg_pa;
239 extern st_entry_t	*Sysseg;
240 extern pt_entry_t	*Sysmap, *Sysptmap;
241 #define	SYSMAP_VA	VM_MAX_KERNEL_ADDRESS
242 extern vsize_t		Sysptsize;
243 extern vsize_t		mem_size;
244 extern vaddr_t		virtual_avail, virtual_end;
245 extern u_int		protection_codes[];
246 #if defined(M68040) || defined(M68060)
247 extern u_int		protostfree;
248 #endif
249 
250 extern char		*vmmap;		/* map for mem, dumps, etc. */
251 extern void		*CADDR1, *CADDR2;
252 extern void		*msgbufaddr;
253 
254 /* for lwp0 uarea initialization after MMU enabled */
255 extern vaddr_t		lwp0uarea;
256 void	pmap_bootstrap_finalize(void);
257 
258 vaddr_t	pmap_map(vaddr_t, paddr_t, paddr_t, int);
259 void	pmap_procwr(struct proc *, vaddr_t, size_t);
260 #define	PMAP_NEED_PROCWR
261 
262 #ifdef CACHE_HAVE_VAC
263 void	pmap_prefer(vaddr_t, vaddr_t *);
264 #define	PMAP_PREFER(foff, vap, sz, td)	pmap_prefer((foff), (vap))
265 #endif
266 
267 void	_pmap_set_page_cacheable(struct pmap *, vaddr_t);
268 void	_pmap_set_page_cacheinhibit(struct pmap *, vaddr_t);
269 int	_pmap_page_is_cacheable(struct pmap *, vaddr_t);
270 
271 #endif /* !_M68K_PMAP_MOTOROLA_H_ */
272