1 /* $NetBSD: m68k.h,v 1.2 1996/09/12 02:52:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 #ifndef _M68K_CPU_H_ 46 #define _M68K_CPU_H_ 47 48 /* 49 * Exported definitions common to Motorola m68k-based ports. 50 * 51 * Note that are some port-specific definitions here, such as 52 * HP and Sun MMU types. These facilitate adding very small 53 * amounts of port-specific code to what would otherwise be 54 * identical. The is especially true in the case of the HP 55 * and other m68k pmaps. 56 * 57 * Individual ports are expected to define the following CPP symbols 58 * in <machine/cpu.h> to enable conditional code: 59 * 60 * M68K_MMU_MOTOROLA Machine has a Motorola MMU (incl. 61 * 68851, 68030, 68040, 68060) 62 * 63 * M68K_MMU_HP Machine has an HP MMU. 64 * 65 * Note also that while m68k-generic code conditionalizes on the 66 * M68K_MMU_HP CPP symbol, none of the HP MMU defintions are in this 67 * file (since none are used in otherwise sharable code). 68 */ 69 70 /* 71 * XXX Much more could be pulled out of port-specific header files 72 * XXX and placed here. 73 */ 74 75 #ifdef _KERNEL 76 /* 77 * All m68k ports must provide these globals. 78 */ 79 extern int cputype; /* CPU on this host */ 80 extern int ectype; /* external cache on this host */ 81 extern int fputype; /* FPU on this host */ 82 extern int mmutype; /* MMU on this host */ 83 #endif 84 85 /* values for cputype */ 86 #define CPU_68020 0 /* 68020 */ 87 #define CPU_68030 1 /* 68030 */ 88 #define CPU_68040 2 /* 68040 */ 89 #define CPU_68060 3 /* 68060 */ 90 91 /* values for ectype */ 92 #define EC_PHYS -1 /* external physical address cache */ 93 #define EC_NONE 0 /* no external cache */ 94 #define EC_VIRT 1 /* external virtual address cache */ 95 96 /* values for fputype */ 97 #define FPU_NONE 0 /* no FPU */ 98 #define FPU_68881 1 /* 68881 FPU */ 99 #define FPU_68882 2 /* 68882 FPU */ 100 #define FPU_68040 3 /* 68040 on-chip FPU */ 101 #define FPU_68060 4 /* 68060 on-chip FPU */ 102 #define FPU_UNKNOWN 5 /* placeholder; unknown FPU */ 103 104 /* values for mmutype (assigned for quick testing) */ 105 #define MMU_68060 -3 /* 68060 on-chip MMU */ 106 #define MMU_68040 -2 /* 68040 on-chip MMU */ 107 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 108 #define MMU_HP 0 /* HP proprietary */ 109 #define MMU_68851 1 /* Motorola 68851 */ 110 #define MMU_SUN 2 /* Sun MMU */ 111 112 /* 113 * 68851 and 68030 MMU 114 */ 115 #define PMMU_LVLMASK 0x0007 116 #define PMMU_INV 0x0400 117 #define PMMU_WP 0x0800 118 #define PMMU_ALV 0x1000 119 #define PMMU_SO 0x2000 120 #define PMMU_LV 0x4000 121 #define PMMU_BE 0x8000 122 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 123 124 /* 125 * 68040 MMU 126 */ 127 #define MMU40_RES 0x001 128 #define MMU40_TTR 0x002 129 #define MMU40_WP 0x004 130 #define MMU40_MOD 0x010 131 #define MMU40_CMMASK 0x060 132 #define MMU40_SUP 0x080 133 #define MMU40_U0 0x100 134 #define MMU40_U1 0x200 135 #define MMU40_GLB 0x400 136 #define MMU40_BE 0x800 137 138 /* 680X0 function codes */ 139 #define FC_USERD 1 /* user data space */ 140 #define FC_USERP 2 /* user program space */ 141 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 142 #define FC_SUPERD 5 /* supervisor data space */ 143 #define FC_SUPERP 6 /* supervisor program space */ 144 #define FC_CPU 7 /* CPU space */ 145 146 /* fields in the 68020 cache control register */ 147 #define IC_ENABLE 0x0001 /* enable instruction cache */ 148 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 149 #define IC_CE 0x0004 /* clear instruction cache entry */ 150 #define IC_CLR 0x0008 /* clear entire instruction cache */ 151 152 /* additional fields in the 68030 cache control register */ 153 #define IC_BE 0x0010 /* instruction burst enable */ 154 #define DC_ENABLE 0x0100 /* data cache enable */ 155 #define DC_FREEZE 0x0200 /* data cache freeze */ 156 #define DC_CE 0x0400 /* clear data cache entry */ 157 #define DC_CLR 0x0800 /* clear entire data cache */ 158 #define DC_BE 0x1000 /* data burst enable */ 159 #define DC_WA 0x2000 /* write allocate */ 160 161 /* fields in the 68040 cache control register */ 162 #define IC40_ENABLE 0x00008000 /* instruction cache enable bit */ 163 #define DC40_ENABLE 0x80000000 /* data cache enable bit */ 164 165 /* additional fields in the 68060 cache control register */ 166 #define DC60_NAD 0x40000000 /* no allocate mode, data cache */ 167 #define DC60_ESB 0x20000000 /* enable store buffer */ 168 #define DC60_DPI 0x10000000 /* disable CPUSH invalidation */ 169 #define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */ 170 171 #define IC60_EBC 0x00800000 /* enable branch cache */ 172 #define IC60_CABC 0x00400000 /* clear all branch cache entries */ 173 #define IC60_CUBC 0x00200000 /* clear user branch cache entries */ 174 175 #define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */ 176 #define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */ 177 178 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 179 #define CACHE_OFF (DC_CLR|IC_CLR) 180 #define CACHE_CLR (CACHE_ON) 181 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 182 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 183 184 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 185 #define CACHE40_OFF (0x00000000) 186 187 #define CACHE60_ON (CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB) 188 #define CACHE60_OFF (CACHE40_OFF|IC60_CABC) 189 190 #endif /* _M68K_CPU_H_ */ 191