1 /* $NetBSD: cacheops_60.h,v 1.1 1997/06/02 20:26:43 leo Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Invalidate entire TLB. 41 */ 42 void TBIA_60 __P((void)); 43 extern inline void 44 TBIA_60() 45 { 46 __asm __volatile (" .word 0xf518" ); /* pflusha */ 47 } 48 49 /* 50 * Invalidate any TLB entry for given VA (TB Invalidate Single) 51 */ 52 void TBIS_60 __P((vm_offset_t)); 53 extern inline void 54 TBIS_60(va) 55 vm_offset_t va; 56 { 57 register vm_offset_t r_va __asm("a0") = va; 58 int tmp; 59 60 __asm __volatile (" movc %1, dfc;" /* select supervisor */ 61 " .word 0xf508;" /* pflush a0@ */ 62 " moveq %3, %1;" /* select user */ 63 " movc %1, dfc;" 64 " .word 0xf508;" /* pflush a0@ */ 65 " movc cacr,%1;" 66 " orl %4,%1;" 67 " movc %1,cacr" : "=d" (tmp) : 68 "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD), 69 "i" (IC60_CABC)); 70 } 71 72 /* 73 * Invalidate supervisor side of TLB 74 */ 75 void TBIAS_60 __P((void)); 76 extern inline void 77 TBIAS_60() 78 { 79 int tmp; 80 /* 81 * Cannot specify supervisor/user on pflusha, so we flush all 82 */ 83 __asm __volatile (" .word 0xf518;" 84 " movc cacr,%0;" 85 " orl %1,%0;" 86 " movc %0,cacr" /* clear all branch cache entries */ 87 : "=d" (tmp) : "i" (IC60_CABC) ); 88 } 89 90 /* 91 * Invalidate user side of TLB 92 */ 93 void TBIAU_60 __P((void)); 94 extern inline void 95 TBIAU_60() 96 { 97 int tmp; 98 /* 99 * Cannot specify supervisor/user on pflusha, so we flush all 100 */ 101 __asm __volatile (" .word 0xf518;" 102 " movc cacr,%0;" 103 " orl %1,%0;" 104 " movc %0,cacr" /* clear all branch cache entries */ 105 : "=d" (tmp) : "i" (IC60_CUBC) ); 106 } 107 108 /* 109 * Invalidate instruction cache 110 */ 111 void ICIA_60 __P((void)); 112 extern inline void 113 ICIA_60() 114 { 115 /* inva ic (also clears branch cache) */ 116 __asm __volatile (" .word 0xf498;"); 117 } 118 119 void ICPA_60 __P((void)); 120 extern inline void 121 ICPA_60() 122 { 123 /* inva ic (also clears branch cache) */ 124 __asm __volatile (" .word 0xf498;"); 125 } 126 127 /* 128 * Invalidate data cache. 129 */ 130 void DCIA_60 __P((void)); 131 extern inline void 132 DCIA_60() 133 { 134 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 135 } 136 137 void DCIS_60 __P((void)); 138 extern inline void 139 DCIS_60() 140 { 141 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 142 } 143 144 void DCIU_60 __P((void)); 145 extern inline void 146 DCIU_60() 147 { 148 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 149 } 150 151 void DCIAS_60 __P((vm_offset_t)); 152 extern inline void 153 DCIAS_60(va) 154 vm_offset_t va; 155 { 156 register vm_offset_t r_va __asm("a0") = va; 157 158 __asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */ 159 } 160 161 void PCIA_60 __P((void)); 162 extern inline void 163 PCIA_60() 164 { 165 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 166 } 167 168 void DCFA_60 __P((void)); 169 extern inline void 170 DCFA_60() 171 { 172 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 173 } 174 175 /* invalidate instruction physical cache line */ 176 void ICPL_60 __P((vm_offset_t)); 177 extern inline void 178 ICPL_60(va) 179 vm_offset_t va; 180 { 181 register vm_offset_t r_va __asm("a0") = va; 182 183 __asm __volatile (" .word 0xf488;" : : "a" (r_va)); /* cinvl ic,a0@ */ 184 } 185 186 /* invalidate instruction physical cache page */ 187 void ICPP_60 __P((vm_offset_t)); 188 extern inline void 189 ICPP_60(va) 190 vm_offset_t va; 191 { 192 register vm_offset_t r_va __asm("a0") = va; 193 194 __asm __volatile (" .word 0xf490;" : : "a" (r_va)); /* cinvp ic,a0@ */ 195 } 196 197 /* invalidate data physical cache line */ 198 void DCPL_60 __P((vm_offset_t)); 199 extern inline void 200 DCPL_60(va) 201 vm_offset_t va; 202 { 203 register vm_offset_t r_va __asm("a0") = va; 204 205 __asm __volatile (" .word 0xf448;" : : "a" (r_va)); /* cinvl dc,a0@ */ 206 } 207 208 /* invalidate data physical cache page */ 209 void DCPP_60 __P((vm_offset_t)); 210 extern inline void 211 DCPP_60(va) 212 vm_offset_t va; 213 { 214 register vm_offset_t r_va __asm("a0") = va; 215 216 __asm __volatile (" .word 0xf450;" : : "a" (r_va)); /* cinvp dc,a0@ */ 217 } 218 219 /* invalidate data physical all */ 220 void DCPA_60 __P((void)); 221 extern inline void 222 DCPA_60() 223 { 224 __asm __volatile (" .word 0xf458;"); /* cinva dc */ 225 } 226 227 /* data cache flush line */ 228 void DCFL_60 __P((vm_offset_t)); 229 extern inline void 230 DCFL_60(va) 231 vm_offset_t va; 232 { 233 register vm_offset_t r_va __asm("a0") = va; 234 235 __asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */ 236 } 237 238 /* data cache flush page */ 239 void DCFP_60 __P((vm_offset_t)); 240 extern inline void 241 DCFP_60(va) 242 vm_offset_t va; 243 { 244 register vm_offset_t r_va __asm("a0") = va; 245 246 __asm __volatile (" .word 0xf470;" : : "a" (r_va)); /* cpushp dc,a0@ */ 247 } 248