1 /* $NetBSD: cacheops_60.h,v 1.6 2005/12/24 20:07:15 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Invalidate entire TLB. 41 */ 42 static inline void __attribute__((__unused__)) 43 TBIA_60(void) 44 { 45 __asm volatile (" .word 0xf518" ); /* pflusha */ 46 } 47 48 /* 49 * Invalidate any TLB entry for given VA (TB Invalidate Single) 50 */ 51 static inline void __attribute__((__unused__)) 52 TBIS_60(vaddr_t va) 53 { 54 register vaddr_t r_va __asm("%a0") = va; 55 int tmp; 56 57 __asm volatile (" movc %1, %%dfc;" /* select supervisor */ 58 " .word 0xf508;" /* pflush %a0@ */ 59 " moveq %3, %1;" /* select user */ 60 " movc %1, %%dfc;" 61 " .word 0xf508;" /* pflush %a0@ */ 62 " movc %%cacr,%1;" 63 " orl %4,%1;" 64 " movc %1,%%cacr" : "=d" (tmp) : 65 "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD), 66 "i" (IC60_CABC)); 67 } 68 69 /* 70 * Invalidate supervisor side of TLB 71 */ 72 static inline void __attribute__((__unused__)) 73 TBIAS_60(void) 74 { 75 int tmp; 76 77 /* 78 * Cannot specify supervisor/user on pflusha, so we flush all 79 */ 80 __asm volatile (" .word 0xf518;" 81 " movc %%cacr,%0;" 82 " orl %1,%0;" 83 " movc %0,%%cacr" /* clear all branch cache 84 entries */ 85 : "=d" (tmp) : "i" (IC60_CABC) ); 86 } 87 88 /* 89 * Invalidate user side of TLB 90 */ 91 static inline void __attribute__((__unused__)) 92 TBIAU_60(void) 93 { 94 int tmp; 95 96 /* 97 * Cannot specify supervisor/user on pflusha, so we flush all 98 */ 99 __asm volatile (" .word 0xf518;" 100 " movc %%cacr,%0;" 101 " orl %1,%0;" 102 " movc %0,%%cacr" /* clear all branch cache 103 entries */ 104 : "=d" (tmp) : "i" (IC60_CUBC) ); 105 } 106 107 /* 108 * Invalidate instruction cache 109 */ 110 static inline void __attribute__((__unused__)) 111 ICIA_60(void) 112 { 113 /* inva ic (also clears branch cache) */ 114 __asm volatile (" .word 0xf498;"); 115 } 116 117 static inline void __attribute__((__unused__)) 118 ICPA_60(void) 119 { 120 /* inva ic (also clears branch cache) */ 121 __asm volatile (" .word 0xf498;"); 122 } 123 124 /* 125 * Invalidate data cache. 126 */ 127 static inline void __attribute__((__unused__)) 128 DCIA_60(void) 129 { 130 __asm volatile (" .word 0xf478;"); /* cpusha dc */ 131 } 132 133 static inline void __attribute__((__unused__)) 134 DCIS_60(void) 135 { 136 __asm volatile (" .word 0xf478;"); /* cpusha dc */ 137 } 138 139 static inline void __attribute__((__unused__)) 140 DCIU_60(void) 141 { 142 __asm volatile (" .word 0xf478;"); /* cpusha dc */ 143 } 144 145 static inline void __attribute__((__unused__)) 146 DCIAS_60(paddr_t pa) 147 { 148 register paddr_t r_pa __asm("%a0") = pa; 149 150 __asm volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ 151 } 152 153 static inline void __attribute__((__unused__)) 154 PCIA_60(void) 155 { 156 __asm volatile (" .word 0xf478;"); /* cpusha dc */ 157 } 158 159 static inline void __attribute__((__unused__)) 160 DCFA_60(void) 161 { 162 __asm volatile (" .word 0xf478;"); /* cpusha dc */ 163 } 164 165 /* invalidate instruction physical cache line */ 166 static inline void __attribute__((__unused__)) 167 ICPL_60(paddr_t pa) 168 { 169 register paddr_t r_pa __asm("%a0") = pa; 170 171 __asm volatile (" .word 0xf488;" : : "a" (r_pa)); /* cinvl ic,%a0@ */ 172 } 173 174 /* invalidate instruction physical cache page */ 175 static inline void __attribute__((__unused__)) 176 ICPP_60(paddr_t pa) 177 { 178 register paddr_t r_pa __asm("%a0") = pa; 179 180 __asm volatile (" .word 0xf490;" : : "a" (r_pa)); /* cinvp ic,%a0@ */ 181 } 182 183 /* invalidate data physical cache line */ 184 static inline void __attribute__((__unused__)) 185 DCPL_60(paddr_t pa) 186 { 187 register paddr_t r_pa __asm("%a0") = pa; 188 189 __asm volatile (" .word 0xf448;" : : "a" (r_pa)); /* cinvl dc,%a0@ */ 190 } 191 192 /* invalidate data physical cache page */ 193 static inline void __attribute__((__unused__)) 194 DCPP_60(paddr_t pa) 195 { 196 register paddr_t r_pa __asm("%a0") = pa; 197 198 __asm volatile (" .word 0xf450;" : : "a" (r_pa)); /* cinvp dc,%a0@ */ 199 } 200 201 /* invalidate data physical all */ 202 static inline void __attribute__((__unused__)) 203 DCPA_60(void) 204 { 205 __asm volatile (" .word 0xf458;"); /* cinva dc */ 206 } 207 208 /* data cache flush line */ 209 static inline void __attribute__((__unused__)) 210 DCFL_60(paddr_t pa) 211 { 212 register paddr_t r_pa __asm("%a0") = pa; 213 214 __asm volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ 215 } 216 217 /* data cache flush page */ 218 static inline void __attribute__((__unused__)) 219 DCFP_60(paddr_t pa) 220 { 221 register paddr_t r_pa __asm("%a0") = pa; 222 223 __asm volatile (" .word 0xf470;" : : "a" (r_pa)); /* cpushp dc,%a0@ */ 224 } 225