1 /* $NetBSD: cacheops_30.h,v 1.1 1997/06/02 20:26:40 leo Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Invalidate entire TLB. 41 */ 42 void TBIA_30 __P((void)); 43 extern inline void 44 TBIA_30() 45 { 46 int tmp = DC_CLEAR; 47 48 __asm __volatile (" pflusha;" 49 " movc %0,cacr" : : "d" (tmp)); 50 } 51 52 /* 53 * Invalidate any TLB entry for given VA (TB Invalidate Single) 54 */ 55 void TBIS_30 __P((vm_offset_t)); 56 extern inline void 57 TBIS_30(va) 58 vm_offset_t va; 59 { 60 __asm __volatile (" pflush #0,#0,%0@;" 61 " movc %1,cacr" : : "a" (va), "d" (DC_CLEAR)); 62 } 63 64 /* 65 * Invalidate supervisor side of TLB 66 */ 67 void TBIAS_30 __P((void)); 68 extern inline void 69 TBIAS_30() 70 { 71 __asm __volatile (" pflush #4,#4;" 72 " movc %0,cacr;" :: "d" (DC_CLEAR)); 73 } 74 75 /* 76 * Invalidate user side of TLB 77 */ 78 void TBIAU_30 __P((void)); 79 extern inline void 80 TBIAU_30() 81 { 82 __asm __volatile (" pflush #0,#4;" 83 " movc %0,cacr;" :: "d" (DC_CLEAR)); 84 } 85 86 /* 87 * Invalidate instruction cache 88 */ 89 void ICIA_30 __P((void)); 90 extern inline void 91 ICIA_30() 92 { 93 __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); 94 } 95 96 void ICPA_30 __P((void)); 97 extern inline void 98 ICPA_30() 99 { 100 __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); 101 } 102 103 /* 104 * Invalidate data cache. 105 * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing 106 * problems with DC_WA. The only cases we have to worry about are context 107 * switch and TLB changes, both of which are handled "in-line" in resume 108 * and TBI*. 109 */ 110 #define DCIA_30() 111 #define DCIS_30() 112 #define DCIU_30() 113 #define DCIAS_30(va) 114 115 116 void PCIA_30 __P((void)); 117 extern inline void 118 PCIA_30() 119 { 120 __asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR)); 121 } 122