1 /* $NetBSD: fpu_implode.c,v 1.2 1996/04/30 11:52:30 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include "ieee.h" 56 #include <machine/reg.h> 57 58 #include "fpu_emulate.h" 59 #include "fpu_arith.h" 60 61 /* Conversion from internal format -- note asymmetry. */ 62 static u_int fpu_ftoi __P((struct fpemu *fe, struct fpn *fp)); 63 static u_int fpu_ftos __P((struct fpemu *fe, struct fpn *fp)); 64 static u_int fpu_ftod __P((struct fpemu *fe, struct fpn *fp, u_int *)); 65 static u_int fpu_ftox __P((struct fpemu *fe, struct fpn *fp, u_int *)); 66 67 /* 68 * Round a number (algorithm from Motorola MC68882 manual, modified for 69 * our internal format). Set inexact exception if rounding is required. 70 * Return true iff we rounded up. 71 * 72 * After rounding, we discard the guard and round bits by shifting right 73 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 74 * This saves effort later. 75 * 76 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 77 * responsibility to fix this if necessary. 78 */ 79 int 80 round(register struct fpemu *fe, register struct fpn *fp) 81 { 82 register u_int m0, m1, m2, m3; 83 register int gr, s; 84 85 m0 = fp->fp_mant[0]; 86 m1 = fp->fp_mant[1]; 87 m2 = fp->fp_mant[2]; 88 m3 = fp->fp_mant[3]; 89 gr = m3 & 3; 90 s = fp->fp_sticky; 91 92 /* mant >>= FP_NG */ 93 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 94 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 95 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 96 m0 >>= FP_NG; 97 98 if ((gr | s) == 0) /* result is exact: no rounding needed */ 99 goto rounddown; 100 101 fe->fe_fpsr |= FPSR_INEX2; /* inexact */ 102 103 /* Go to rounddown to round down; break to round up. */ 104 switch (fe->fe_fpcr & FPCR_ROUND) { 105 106 case FPCR_NEAR: 107 default: 108 /* 109 * Round only if guard is set (gr & 2). If guard is set, 110 * but round & sticky both clear, then we want to round 111 * but have a tie, so round to even, i.e., add 1 iff odd. 112 */ 113 if ((gr & 2) == 0) 114 goto rounddown; 115 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 116 break; 117 goto rounddown; 118 119 case FPCR_ZERO: 120 /* Round towards zero, i.e., down. */ 121 goto rounddown; 122 123 case FPCR_MINF: 124 /* Round towards -Inf: up if negative, down if positive. */ 125 if (fp->fp_sign) 126 break; 127 goto rounddown; 128 129 case FPCR_PINF: 130 /* Round towards +Inf: up if positive, down otherwise. */ 131 if (!fp->fp_sign) 132 break; 133 goto rounddown; 134 } 135 136 /* Bump low bit of mantissa, with carry. */ 137 #ifdef sparc /* ``cheating'' (left out FPU_DECL_CARRY; know this is faster) */ 138 FPU_ADDS(m3, m3, 1); 139 FPU_ADDCS(m2, m2, 0); 140 FPU_ADDCS(m1, m1, 0); 141 FPU_ADDC(m0, m0, 0); 142 #else 143 if (++m3 == 0 && ++m2 == 0 && ++m1 == 0) 144 m0++; 145 #endif 146 fp->fp_mant[0] = m0; 147 fp->fp_mant[1] = m1; 148 fp->fp_mant[2] = m2; 149 fp->fp_mant[3] = m3; 150 return (1); 151 152 rounddown: 153 fp->fp_mant[0] = m0; 154 fp->fp_mant[1] = m1; 155 fp->fp_mant[2] = m2; 156 fp->fp_mant[3] = m3; 157 return (0); 158 } 159 160 /* 161 * For overflow: return true if overflow is to go to +/-Inf, according 162 * to the sign of the overflowing result. If false, overflow is to go 163 * to the largest magnitude value instead. 164 */ 165 static int 166 toinf(struct fpemu *fe, int sign) 167 { 168 int inf; 169 170 /* look at rounding direction */ 171 switch (fe->fe_fpcr & FPCR_ROUND) { 172 173 default: 174 case FPCR_NEAR: /* the nearest value is always Inf */ 175 inf = 1; 176 break; 177 178 case FPCR_ZERO: /* toward 0 => never towards Inf */ 179 inf = 0; 180 break; 181 182 case FPCR_PINF: /* toward +Inf iff positive */ 183 inf = (sign == 0); 184 break; 185 186 case FPCR_MINF: /* toward -Inf iff negative */ 187 inf = sign; 188 break; 189 } 190 return (inf); 191 } 192 193 /* 194 * fpn -> int (int value returned as return value). 195 * 196 * N.B.: this conversion always rounds towards zero (this is a peculiarity 197 * of the SPARC instruction set). 198 */ 199 static u_int 200 fpu_ftoi(fe, fp) 201 struct fpemu *fe; 202 register struct fpn *fp; 203 { 204 register u_int i; 205 register int sign, exp; 206 207 sign = fp->fp_sign; 208 switch (fp->fp_class) { 209 210 case FPC_ZERO: 211 return (0); 212 213 case FPC_NUM: 214 /* 215 * If exp >= 2^32, overflow. Otherwise shift value right 216 * into last mantissa word (this will not exceed 0xffffffff), 217 * shifting any guard and round bits out into the sticky 218 * bit. Then ``round'' towards zero, i.e., just set an 219 * inexact exception if sticky is set (see round()). 220 * If the result is > 0x80000000, or is positive and equals 221 * 0x80000000, overflow; otherwise the last fraction word 222 * is the result. 223 */ 224 if ((exp = fp->fp_exp) >= 32) 225 break; 226 /* NB: the following includes exp < 0 cases */ 227 if (fpu_shr(fp, FP_NMANT - 1 - FP_NG - exp) != 0) 228 /* m68881/2 do not underflow when 229 converting to integer */; 230 round(fe, fp); 231 i = fp->fp_mant[3]; 232 if (i >= ((u_int)0x80000000 + sign)) 233 break; 234 return (sign ? -i : i); 235 236 default: /* Inf, qNaN, sNaN */ 237 break; 238 } 239 /* overflow: replace any inexact exception with invalid */ 240 fe->fe_fpsr = (fe->fe_fpsr & ~FPSR_INEX2) | FPSR_OPERR; 241 return (0x7fffffff + sign); 242 } 243 244 /* 245 * fpn -> single (32 bit single returned as return value). 246 * We assume <= 29 bits in a single-precision fraction (1.f part). 247 */ 248 static u_int 249 fpu_ftos(fe, fp) 250 struct fpemu *fe; 251 register struct fpn *fp; 252 { 253 register u_int sign = fp->fp_sign << 31; 254 register int exp; 255 256 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 257 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 258 259 /* Take care of non-numbers first. */ 260 if (ISNAN(fp)) { 261 /* 262 * Preserve upper bits of NaN, per SPARC V8 appendix N. 263 * Note that fp->fp_mant[0] has the quiet bit set, 264 * even if it is classified as a signalling NaN. 265 */ 266 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 267 exp = SNG_EXP_INFNAN; 268 goto done; 269 } 270 if (ISINF(fp)) 271 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 272 if (ISZERO(fp)) 273 return (sign); 274 275 /* 276 * Normals (including subnormals). Drop all the fraction bits 277 * (including the explicit ``implied'' 1 bit) down into the 278 * single-precision range. If the number is subnormal, move 279 * the ``implied'' 1 into the explicit range as well, and shift 280 * right to introduce leading zeroes. Rounding then acts 281 * differently for normals and subnormals: the largest subnormal 282 * may round to the smallest normal (1.0 x 2^minexp), or may 283 * remain subnormal. In the latter case, signal an underflow 284 * if the result was inexact or if underflow traps are enabled. 285 * 286 * Rounding a normal, on the other hand, always produces another 287 * normal (although either way the result might be too big for 288 * single precision, and cause an overflow). If rounding a 289 * normal produces 2.0 in the fraction, we need not adjust that 290 * fraction at all, since both 1.0 and 2.0 are zero under the 291 * fraction mask. 292 * 293 * Note that the guard and round bits vanish from the number after 294 * rounding. 295 */ 296 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 297 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 298 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 299 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 300 return (sign | SNG_EXP(1) | 0); 301 if (fe->fe_fpsr & FPSR_INEX2) 302 /* mc68881/2 don't underflow when converting */; 303 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 304 } 305 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 306 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 307 #ifdef DIAGNOSTIC 308 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 309 panic("fpu_ftos"); 310 #endif 311 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 312 exp++; 313 if (exp >= SNG_EXP_INFNAN) { 314 /* overflow to inf or to max single */ 315 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2; 316 if (toinf(fe, sign)) 317 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 318 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 319 } 320 done: 321 /* phew, made it */ 322 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 323 } 324 325 /* 326 * fpn -> double (32 bit high-order result returned; 32-bit low order result 327 * left in res[1]). Assumes <= 61 bits in double precision fraction. 328 * 329 * This code mimics fpu_ftos; see it for comments. 330 */ 331 static u_int 332 fpu_ftod(fe, fp, res) 333 struct fpemu *fe; 334 register struct fpn *fp; 335 u_int *res; 336 { 337 register u_int sign = fp->fp_sign << 31; 338 register int exp; 339 340 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 341 #define DBL_MASK (DBL_EXP(1) - 1) 342 343 if (ISNAN(fp)) { 344 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 345 exp = DBL_EXP_INFNAN; 346 goto done; 347 } 348 if (ISINF(fp)) { 349 sign |= DBL_EXP(DBL_EXP_INFNAN); 350 res[1] = 0; 351 return (sign); 352 } 353 if (ISZERO(fp)) { 354 res[1] = 0; 355 return (sign); 356 } 357 358 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 359 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 360 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 361 res[1] = 0; 362 return (sign | DBL_EXP(1) | 0); 363 } 364 if (fe->fe_fpsr & FPSR_INEX2) 365 /* mc68881/2 don't underflow when converting */; 366 exp = 0; 367 goto done; 368 } 369 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 370 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 371 exp++; 372 if (exp >= DBL_EXP_INFNAN) { 373 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2; 374 if (toinf(fe, sign)) { 375 res[1] = 0; 376 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 377 } 378 res[1] = ~0; 379 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 380 } 381 done: 382 res[1] = fp->fp_mant[3]; 383 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 384 } 385 386 /* 387 * fpn -> 68k extended (32 bit high-order result returned; two 32-bit low 388 * order result left in res[1] & res[2]). Assumes == 64 bits in extended 389 * precision fraction. 390 * 391 * This code mimics fpu_ftos; see it for comments. 392 */ 393 static u_int 394 fpu_ftox(fe, fp, res) 395 struct fpemu *fe; 396 register struct fpn *fp; 397 u_int *res; 398 { 399 register u_int sign = fp->fp_sign << 31; 400 register int exp; 401 402 #define EXT_EXP(e) ((e) << 16) 403 #define EXT_MASK (EXT_EXP(1) - 1) 404 405 if (ISNAN(fp)) { 406 (void) fpu_shr(fp, FP_NMANT - 1 - EXT_FRACBITS); 407 exp = EXT_EXP_INFNAN; 408 goto done; 409 } 410 if (ISINF(fp)) { 411 sign |= EXT_EXP(EXT_EXP_INFNAN); 412 res[1] = res[2] = 0; 413 return (sign); 414 } 415 if (ISZERO(fp)) { 416 res[1] = res[2] = 0; 417 return (sign); 418 } 419 420 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 421 /* I'm not sure about this <=... exp==0 doesn't mean 422 it's a denormal in extended format */ 423 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 424 if (round(fe, fp) && fp->fp_mant[2] == EXT_EXP(1)) { 425 res[1] = res[2] = 0; 426 return (sign | EXT_EXP(1) | 0); 427 } 428 if (fe->fe_fpsr & FPSR_INEX2) 429 /* mc68881/2 don't underflow */; 430 exp = 0; 431 goto done; 432 } 433 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS); 434 if (round(fe, fp) && fp->fp_mant[2] == EXT_EXP(2)) 435 exp++; 436 if (exp >= EXT_EXP_INFNAN) { 437 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2; 438 if (toinf(fe, sign)) { 439 res[1] = res[2] = 0; 440 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 441 } 442 res[1] = res[2] = ~0; 443 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 444 } 445 done: 446 res[1] = fp->fp_mant[2]; 447 res[2] = fp->fp_mant[3]; 448 return (sign | EXT_EXP(exp)); 449 } 450 451 /* 452 * Implode an fpn, writing the result into the given space. 453 */ 454 void 455 fpu_implode(fe, fp, type, space) 456 struct fpemu *fe; 457 register struct fpn *fp; 458 int type; 459 register u_int *space; 460 { 461 fe->fe_fpsr &= ~FPSR_EXCP; 462 463 switch (type) { 464 case FTYPE_LNG: 465 space[0] = fpu_ftoi(fe, fp); 466 break; 467 468 case FTYPE_SNG: 469 space[0] = fpu_ftos(fe, fp); 470 break; 471 472 case FTYPE_DBL: 473 space[0] = fpu_ftod(fe, fp, space); 474 break; 475 476 case FTYPE_EXT: 477 /* funky rounding precision options ?? */ 478 space[0] = fpu_ftox(fe, fp, space); 479 break; 480 481 default: 482 panic("fpu_implode"); 483 } 484 } 485