1 /* $NetBSD: fpu_fscale.c,v 1.11 2003/07/15 02:43:10 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: fpu_fscale.c,v 1.11 2003/07/15 02:43:10 lukem Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/signal.h> 45 #include <sys/systm.h> 46 #include <machine/frame.h> 47 48 #include "fpu_emulate.h" 49 50 int 51 fpu_emul_fscale(fe, insn) 52 struct fpemu *fe; 53 struct instruction *insn; 54 { 55 struct frame *frame; 56 u_int *fpregs; 57 int word1, sig; 58 int regnum, format; 59 int scale, sign, exp; 60 u_int m0, m1; 61 u_int buf[3], fpsr; 62 #if DEBUG_FPE 63 int flags; 64 char regname; 65 #endif 66 67 scale = sig = 0; 68 frame = fe->fe_frame; 69 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 70 /* clear all exceptions and conditions */ 71 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 72 #if DEBUG_FPE 73 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 74 #endif 75 76 word1 = insn->is_word1; 77 format = (word1 >> 10) & 7; 78 regnum = (word1 >> 7) & 7; 79 80 fe->fe_fpcr &= FPCR_ROUND; 81 fe->fe_fpcr |= FPCR_ZERO; 82 83 /* get the source operand */ 84 if ((word1 & 0x4000) == 0) { 85 #if DEBUG_FPE 86 printf("fpu_emul_fscale: FP%d op FP%d => FP%d\n", 87 format, regnum, regnum); 88 /* the operand is an FP reg */ 89 printf("fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 90 format, fpregs[format*3], fpregs[format*3+1], 91 fpregs[format*3+2]); 92 #endif 93 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 94 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 95 scale = buf[0]; 96 } else { 97 /* the operand is in memory */ 98 if (format == FTYPE_DBL) { 99 insn->is_datasize = 8; 100 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 101 insn->is_datasize = 4; 102 } else if (format == FTYPE_WRD) { 103 insn->is_datasize = 2; 104 } else if (format == FTYPE_BYT) { 105 insn->is_datasize = 1; 106 } else if (format == FTYPE_EXT) { 107 insn->is_datasize = 12; 108 } else { 109 /* invalid or unsupported operand format */ 110 sig = SIGFPE; 111 return sig; 112 } 113 114 /* Get effective address. (modreg=opcode&077) */ 115 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 116 if (sig) { 117 #if DEBUG_FPE 118 printf("fpu_emul_fscale: error in decode_ea\n"); 119 #endif 120 return sig; 121 } 122 123 #if DEBUG_FPE 124 printf("fpu_emul_fscale: addr mode = "); 125 flags = insn->is_ea.ea_flags; 126 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 127 128 if (flags & EA_DIRECT) { 129 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7); 130 } else if (flags & EA_PREDECR) { 131 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7); 132 } else if (flags & EA_POSTINCR) { 133 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 134 } else if (flags & EA_OFFSET) { 135 printf("%c%d@(%d)\n", regname, insn->is_ea.ea_regnum & 7, 136 insn->is_ea.ea_offset); 137 } else if (flags & EA_INDEXED) { 138 printf("%c%d@(...)\n", regname, insn->is_ea.ea_regnum & 7); 139 } else if (flags & EA_ABS) { 140 printf("0x%08x\n", insn->is_ea.ea_absaddr); 141 } else if (flags & EA_PC_REL) { 142 printf("pc@(%d)\n", insn->is_ea.ea_offset); 143 } else if (flags & EA_IMMED) { 144 printf("#0x%08x%08x%08x\n", 145 insn->is_ea.ea_immed[0], insn->is_ea.ea_immed[1], 146 insn->is_ea.ea_immed[2]); 147 } else { 148 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 149 } 150 #endif 151 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 152 153 #if DEBUG_FPE 154 printf("fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 155 buf[0], buf[1], buf[2], insn->is_datasize); 156 #endif 157 if (format == FTYPE_LNG) { 158 /* nothing */ 159 scale = buf[0]; 160 } else if (format == FTYPE_WRD) { 161 /* sign-extend */ 162 scale = buf[0] & 0xffff; 163 if (scale & 0x8000) { 164 scale |= 0xffff0000; 165 } 166 } else if (format == FTYPE_BYT) { 167 /* sign-extend */ 168 scale = buf[0] & 0xff; 169 if (scale & 0x80) { 170 scale |= 0xffffff00; 171 } 172 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 173 format == FTYPE_EXT) { 174 fpu_explode(fe, &fe->fe_f2, format, buf); 175 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 176 scale = buf[0]; 177 } 178 /* make it look like we've got an FP oprand */ 179 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 180 } 181 182 /* assume there's no exception */ 183 sig = 0; 184 185 /* it's barbaric but we're going to operate directly on 186 * the dst operand's bit pattern */ 187 sign = fpregs[regnum * 3] & 0x80000000; 188 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 189 m0 = fpregs[regnum * 3 + 1]; 190 m1 = fpregs[regnum * 3 + 2]; 191 192 switch (fe->fe_f2.fp_class) { 193 case FPC_SNAN: 194 fpsr |= FPSR_SNAN; 195 case FPC_QNAN: 196 /* dst = NaN */ 197 exp = 0x7fff; 198 m0 = m1 = 0xffffffff; 199 break; 200 case FPC_ZERO: 201 case FPC_NUM: 202 if ((0 < exp && exp < 0x7fff) || 203 (exp == 0 && (m0 | m1) != 0)) { 204 /* normal or denormal */ 205 exp += scale; 206 if (exp < 0) { 207 /* underflow */ 208 u_int grs; /* guard, round and sticky */ 209 210 exp = 0; 211 grs = m1 << (32 + exp); 212 m1 = m0 << (32 + exp) | m1 >> -exp; 213 m0 >>= -exp; 214 if (grs != 0) { 215 fpsr |= FPSR_INEX2; 216 217 switch (fe->fe_fpcr & 0x30) { 218 case FPCR_MINF: 219 if (sign != 0) { 220 if (++m1 == 0 && 221 ++m0 == 0) { 222 m0 = 0x80000000; 223 exp++; 224 } 225 } 226 break; 227 case FPCR_NEAR: 228 if (grs == 0x80000000) { 229 /* tie */ 230 if ((m1 & 1) && 231 ++m1 == 0 && 232 ++m0 == 0) { 233 m0 = 0x80000000; 234 exp++; 235 } 236 } else if (grs & 0x80000000) { 237 if (++m1 == 0 && 238 ++m0 == 0) { 239 m0 = 0x80000000; 240 exp++; 241 } 242 } 243 break; 244 case FPCR_PINF: 245 if (sign == 0) { 246 if (++m1 == 0 && 247 ++m0 == 0) { 248 m0 = 0x80000000; 249 exp++; 250 } 251 } 252 break; 253 case FPCR_ZERO: 254 break; 255 } 256 } 257 if (exp == 0 && (m0 & 0x80000000) == 0) { 258 fpsr |= FPSR_UNFL; 259 if ((m0 | m1) == 0) { 260 fpsr |= FPSR_ZERO; 261 } 262 } 263 } else if (exp >= 0x7fff) { 264 /* overflow --> result = Inf */ 265 /* but first, try to normalize in case it's an unnormalized */ 266 while ((m0 & 0x80000000) == 0) { 267 exp--; 268 m0 = (m0 << 1) | (m1 >> 31); 269 m1 = m1 << 1; 270 } 271 /* if it's still too large, then return Inf */ 272 if (exp >= 0x7fff) { 273 exp = 0x7fff; 274 m0 = m1 = 0; 275 fpsr |= FPSR_OVFL | FPSR_INF; 276 } 277 } else if ((m0 & 0x80000000) == 0) { 278 /* 279 * it's a denormal; we try to normalize but 280 * result may and may not be a normal. 281 */ 282 while (exp > 0 && (m0 & 0x80000000) == 0) { 283 exp--; 284 m0 = (m0 << 1) | (m1 >> 31); 285 m1 = m1 << 1; 286 } 287 if ((m0 & 0x80000000) == 0) { 288 fpsr |= FPSR_UNFL; 289 } 290 } /* exp in range and mantissa normalized */ 291 } else if (exp == 0 && m0 == 0 && m1 == 0) { 292 /* dst is Zero */ 293 fpsr |= FPSR_ZERO; 294 } /* else we know exp == 0x7fff */ 295 else if ((m0 | m1) == 0) { 296 fpsr |= FPSR_INF; 297 } else if ((m0 & 0x40000000) == 0) { 298 /* a signaling NaN */ 299 fpsr |= FPSR_NAN | FPSR_SNAN; 300 } else { 301 /* a quiet NaN */ 302 fpsr |= FPSR_NAN; 303 } 304 break; 305 case FPC_INF: 306 /* dst = NaN */ 307 exp = 0x7fff; 308 m0 = m1 = 0xffffffff; 309 fpsr |= FPSR_OPERR | FPSR_NAN; 310 break; 311 default: 312 #ifdef DEBUG 313 panic("fpu_emul_fscale: invalid fp class"); 314 #endif 315 break; 316 } 317 318 /* store the result */ 319 fpregs[regnum * 3] = sign | (exp << 16); 320 fpregs[regnum * 3 + 1] = m0; 321 fpregs[regnum * 3 + 2] = m1; 322 323 if (sign) { 324 fpsr |= FPSR_NEG; 325 } 326 327 /* update fpsr according to the result of operation */ 328 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 329 330 #if DEBUG_FPE 331 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 332 fe->fe_fpsr, fe->fe_fpcr); 333 #endif 334 335 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 336 } 337