1 /* $NetBSD: fpu_fscale.c,v 1.16 2013/03/26 11:30:20 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: fpu_fscale.c,v 1.16 2013/03/26 11:30:20 isaki Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/signal.h> 45 #include <sys/systm.h> 46 #include <machine/frame.h> 47 48 #include "fpu_emulate.h" 49 50 int 51 fpu_emul_fscale(struct fpemu *fe, struct instruction *insn) 52 { 53 struct frame *frame; 54 uint32_t *fpregs; 55 int word1, sig; 56 int regnum, format; 57 int scale, sign, exp; 58 uint32_t m0, m1; 59 uint32_t buf[3], fpsr; 60 #if DEBUG_FPE 61 int flags; 62 char regname; 63 #endif 64 65 scale = sig = 0; 66 frame = fe->fe_frame; 67 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 68 /* clear all exceptions and conditions */ 69 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 70 #if DEBUG_FPE 71 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 72 #endif 73 74 word1 = insn->is_word1; 75 format = (word1 >> 10) & 7; 76 regnum = (word1 >> 7) & 7; 77 78 fe->fe_fpcr &= FPCR_ROUND; 79 fe->fe_fpcr |= FPCR_ZERO; 80 81 /* get the source operand */ 82 if ((word1 & 0x4000) == 0) { 83 #if DEBUG_FPE 84 printf("fpu_emul_fscale: FP%d op FP%d => FP%d\n", 85 format, regnum, regnum); 86 /* the operand is an FP reg */ 87 printf("fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 88 format, fpregs[format*3], fpregs[format*3+1], 89 fpregs[format*3+2]); 90 #endif 91 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 92 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 93 scale = buf[0]; 94 } else { 95 /* the operand is in memory */ 96 if (format == FTYPE_DBL) { 97 insn->is_datasize = 8; 98 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 99 insn->is_datasize = 4; 100 } else if (format == FTYPE_WRD) { 101 insn->is_datasize = 2; 102 } else if (format == FTYPE_BYT) { 103 insn->is_datasize = 1; 104 } else if (format == FTYPE_EXT) { 105 insn->is_datasize = 12; 106 } else { 107 /* invalid or unsupported operand format */ 108 sig = SIGFPE; 109 return sig; 110 } 111 112 /* Get effective address. (modreg=opcode&077) */ 113 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 114 if (sig) { 115 #if DEBUG_FPE 116 printf("fpu_emul_fscale: error in decode_ea\n"); 117 #endif 118 return sig; 119 } 120 121 #if DEBUG_FPE 122 printf("fpu_emul_fscale: addr mode = "); 123 flags = insn->is_ea.ea_flags; 124 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 125 126 if (flags & EA_DIRECT) { 127 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7); 128 } else if (flags & EA_PREDECR) { 129 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7); 130 } else if (flags & EA_POSTINCR) { 131 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 132 } else if (flags & EA_OFFSET) { 133 printf("%c%d@(%d)\n", 134 regname, insn->is_ea.ea_regnum & 7, 135 insn->is_ea.ea_offset); 136 } else if (flags & EA_INDEXED) { 137 printf("%c%d@(...)\n", 138 regname, insn->is_ea.ea_regnum & 7); 139 } else if (flags & EA_ABS) { 140 printf("0x%08x\n", insn->is_ea.ea_absaddr); 141 } else if (flags & EA_PC_REL) { 142 printf("pc@(%d)\n", insn->is_ea.ea_offset); 143 } else if (flags & EA_IMMED) { 144 printf("#0x%08x%08x%08x\n", 145 insn->is_ea.ea_immed[0], 146 insn->is_ea.ea_immed[1], 147 insn->is_ea.ea_immed[2]); 148 } else { 149 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 150 } 151 #endif 152 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 153 154 #if DEBUG_FPE 155 printf("fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 156 buf[0], buf[1], buf[2], insn->is_datasize); 157 #endif 158 if (format == FTYPE_LNG) { 159 /* nothing */ 160 scale = buf[0]; 161 } else if (format == FTYPE_WRD) { 162 /* sign-extend */ 163 scale = buf[0] & 0xffff; 164 if (scale & 0x8000) { 165 scale |= 0xffff0000; 166 } 167 } else if (format == FTYPE_BYT) { 168 /* sign-extend */ 169 scale = buf[0] & 0xff; 170 if (scale & 0x80) { 171 scale |= 0xffffff00; 172 } 173 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 174 format == FTYPE_EXT) { 175 fpu_explode(fe, &fe->fe_f2, format, buf); 176 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 177 scale = buf[0]; 178 } 179 /* make it look like we've got an FP oprand */ 180 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 181 } 182 183 /* assume there's no exception */ 184 sig = 0; 185 186 /* 187 * it's barbaric but we're going to operate directly on 188 * the dst operand's bit pattern 189 */ 190 sign = fpregs[regnum * 3] & 0x80000000; 191 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 192 m0 = fpregs[regnum * 3 + 1]; 193 m1 = fpregs[regnum * 3 + 2]; 194 195 switch (fe->fe_f2.fp_class) { 196 case FPC_SNAN: 197 fpsr |= FPSR_SNAN; 198 case FPC_QNAN: 199 /* dst = NaN */ 200 exp = 0x7fff; 201 m0 = m1 = 0xffffffff; 202 break; 203 case FPC_ZERO: 204 case FPC_NUM: 205 if ((0 < exp && exp < 0x7fff) || 206 (exp == 0 && (m0 | m1) != 0)) { 207 /* normal or denormal */ 208 exp += scale; 209 if (exp < 0) { 210 /* underflow */ 211 uint32_t grs; /* guard, round and sticky */ 212 213 exp = 0; 214 grs = m1 << (32 + exp); 215 m1 = m0 << (32 + exp) | m1 >> -exp; 216 m0 >>= -exp; 217 if (grs != 0) { 218 fpsr |= FPSR_INEX2; 219 220 switch (fe->fe_fpcr & 0x30) { 221 case FPCR_MINF: 222 if (sign != 0) { 223 if (++m1 == 0 && 224 ++m0 == 0) { 225 m0 = 0x80000000; 226 exp++; 227 } 228 } 229 break; 230 case FPCR_NEAR: 231 if (grs == 0x80000000) { 232 /* tie */ 233 if ((m1 & 1) && 234 ++m1 == 0 && 235 ++m0 == 0) { 236 m0 = 0x80000000; 237 exp++; 238 } 239 } else if (grs & 0x80000000) { 240 if (++m1 == 0 && 241 ++m0 == 0) { 242 m0 = 0x80000000; 243 exp++; 244 } 245 } 246 break; 247 case FPCR_PINF: 248 if (sign == 0) { 249 if (++m1 == 0 && 250 ++m0 == 0) { 251 m0 = 0x80000000; 252 exp++; 253 } 254 } 255 break; 256 case FPCR_ZERO: 257 break; 258 } 259 } 260 if (exp == 0 && (m0 & 0x80000000) == 0) { 261 fpsr |= FPSR_UNFL; 262 if ((m0 | m1) == 0) { 263 fpsr |= FPSR_ZERO; 264 } 265 } 266 } else if (exp >= 0x7fff) { 267 /* overflow --> result = Inf */ 268 /* 269 * but first, try to normalize in case it's an 270 * unnormalized 271 */ 272 while ((m0 & 0x80000000) == 0) { 273 exp--; 274 m0 = (m0 << 1) | (m1 >> 31); 275 m1 = m1 << 1; 276 } 277 /* if it's still too large, then return Inf */ 278 if (exp >= 0x7fff) { 279 exp = 0x7fff; 280 m0 = m1 = 0; 281 fpsr |= FPSR_OVFL | FPSR_INF; 282 } 283 } else if ((m0 & 0x80000000) == 0) { 284 /* 285 * it's a denormal; we try to normalize but 286 * result may and may not be a normal. 287 */ 288 while (exp > 0 && (m0 & 0x80000000) == 0) { 289 exp--; 290 m0 = (m0 << 1) | (m1 >> 31); 291 m1 = m1 << 1; 292 } 293 if ((m0 & 0x80000000) == 0) { 294 fpsr |= FPSR_UNFL; 295 } 296 } /* exp in range and mantissa normalized */ 297 } else if (exp == 0 && m0 == 0 && m1 == 0) { 298 /* dst is Zero */ 299 fpsr |= FPSR_ZERO; 300 } /* else we know exp == 0x7fff */ 301 else if ((m0 | m1) == 0) { 302 fpsr |= FPSR_INF; 303 } else if ((m0 & 0x40000000) == 0) { 304 /* a signaling NaN */ 305 fpsr |= FPSR_NAN | FPSR_SNAN; 306 } else { 307 /* a quiet NaN */ 308 fpsr |= FPSR_NAN; 309 } 310 break; 311 case FPC_INF: 312 /* dst = NaN */ 313 exp = 0x7fff; 314 m0 = m1 = 0xffffffff; 315 fpsr |= FPSR_OPERR | FPSR_NAN; 316 break; 317 default: 318 #ifdef DEBUG 319 panic("fpu_emul_fscale: invalid fp class"); 320 #endif 321 break; 322 } 323 324 /* store the result */ 325 fpregs[regnum * 3] = sign | (exp << 16); 326 fpregs[regnum * 3 + 1] = m0; 327 fpregs[regnum * 3 + 2] = m1; 328 329 if (sign) { 330 fpsr |= FPSR_NEG; 331 } 332 333 /* update fpsr according to the result of operation */ 334 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 335 336 #if DEBUG_FPE 337 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 338 fe->fe_fpsr, fe->fe_fpcr); 339 #endif 340 341 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 342 } 343