xref: /netbsd-src/sys/arch/ia64/include/dig64.h (revision 1c4208385cbed43d63c31ced5f384bd0e488ed2e)
1*1c420838Sandvar /*	$NetBSD: dig64.h,v 1.4 2022/07/21 14:27:46 andvar Exp $	*/
2ba7cbe76Scherry 
3ba7cbe76Scherry /*-
4ba7cbe76Scherry  * Copyright (c) 2002 Marcel Moolenaar
5ba7cbe76Scherry  * All rights reserved.
6ba7cbe76Scherry  *
7ba7cbe76Scherry  * Redistribution and use in source and binary forms, with or without
8ba7cbe76Scherry  * modification, are permitted provided that the following conditions
9ba7cbe76Scherry  * are met:
10ba7cbe76Scherry  *
11ba7cbe76Scherry  * 1. Redistributions of source code must retain the above copyright
12ba7cbe76Scherry  *    notice, this list of conditions and the following disclaimer.
13ba7cbe76Scherry  * 2. Redistributions in binary form must reproduce the above copyright
14ba7cbe76Scherry  *    notice, this list of conditions and the following disclaimer in the
15ba7cbe76Scherry  *    documentation and/or other materials provided with the distribution.
16ba7cbe76Scherry  *
17ba7cbe76Scherry  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18ba7cbe76Scherry  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19ba7cbe76Scherry  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20ba7cbe76Scherry  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21ba7cbe76Scherry  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22ba7cbe76Scherry  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23ba7cbe76Scherry  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24ba7cbe76Scherry  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25ba7cbe76Scherry  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26ba7cbe76Scherry  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27ba7cbe76Scherry  *
28ba7cbe76Scherry  * $FreeBSD$
29ba7cbe76Scherry  */
30ba7cbe76Scherry 
31ba7cbe76Scherry #ifndef _MACHINE_DIG64_H_
32ba7cbe76Scherry #define	_MACHINE_DIG64_H_
33ba7cbe76Scherry 
34833b1484Skiyohara /*
356913cbefSandvar  * This header file written refer to 'DIG64 Descriptions for Primary Console &
36833b1484Skiyohara  * Debug Port Devices'.
37833b1484Skiyohara  */
38833b1484Skiyohara 
39833b1484Skiyohara /* ACPI GAS (Generic Address Structure) */
40ba7cbe76Scherry struct dig64_gas {
41ba7cbe76Scherry 	uint8_t		addr_space;
42ba7cbe76Scherry 	uint8_t		bit_width;
43ba7cbe76Scherry 	uint8_t		bit_offset;
44ba7cbe76Scherry 	uint8_t		_reserved_;
45ba7cbe76Scherry 	/*
46ba7cbe76Scherry 	 * XXX using a 64-bit type for the address would cause padding and
47ba7cbe76Scherry 	 * using __packed would cause unaligned accesses...
48ba7cbe76Scherry 	 */
49ba7cbe76Scherry 	uint32_t	addr_low;
50ba7cbe76Scherry 	uint32_t	addr_high;
51ba7cbe76Scherry };
52ba7cbe76Scherry 
53ba7cbe76Scherry struct dig64_hcdp_entry {
54ba7cbe76Scherry 	uint8_t		type;
55833b1484Skiyohara #define	DIG64_HCDP_CONSOLE		DIG64_ENTRYTYPE_TYPE0
56833b1484Skiyohara #define	DIG64_HCDP_DBGPORT		DIG64_ENTRYTYPE_TYPE1
57ba7cbe76Scherry 	uint8_t		databits;
58ba7cbe76Scherry 	uint8_t		parity;
59833b1484Skiyohara #define	DIG64_HCDP_PARITY_NO		1
60833b1484Skiyohara #define	DIG64_HCDP_PARITY_EVEN		2
61833b1484Skiyohara #define	DIG64_HCDP_PARITY_ODD		3
62833b1484Skiyohara #define	DIG64_HCDP_PARITY_MARK		4
63833b1484Skiyohara #define	DIG64_HCDP_PARITY_SPACE		5
64ba7cbe76Scherry 	uint8_t		stopbits;
65833b1484Skiyohara #define	DIG64_HCDP_STOPBITS_1		1
66833b1484Skiyohara #define	DIG64_HCDP_STOPBITS_15		2
67833b1484Skiyohara #define	DIG64_HCDP_STOPBITS_2		3
68ba7cbe76Scherry 	uint8_t		pci_segment;
69ba7cbe76Scherry 	uint8_t		pci_bus;
70ba7cbe76Scherry 	uint8_t		pci_device:5;
71ba7cbe76Scherry 	uint8_t		_reserved1_:3;
72ba7cbe76Scherry 	uint8_t		pci_function:3;
73ba7cbe76Scherry 	uint8_t		_reserved2_:3;
74ba7cbe76Scherry 	uint8_t		interrupt:1;
75ba7cbe76Scherry 	uint8_t		pci_flag:1;
76ba7cbe76Scherry 	/*
77ba7cbe76Scherry 	 * XXX using a 64-bit type for the baudrate would cause padding and
78ba7cbe76Scherry 	 * using __packed would cause unaligned accesses...
79ba7cbe76Scherry 	 */
80ba7cbe76Scherry 	uint32_t	baud_low;
81ba7cbe76Scherry 	uint32_t	baud_high;
82ba7cbe76Scherry 	struct dig64_gas address;
83ba7cbe76Scherry 	uint16_t	pci_devid;
84ba7cbe76Scherry 	uint16_t	pci_vendor;
85ba7cbe76Scherry 	uint32_t	irq;
86ba7cbe76Scherry 	uint32_t	pclock;
87ba7cbe76Scherry 	uint8_t		pci_interface;
88ba7cbe76Scherry 	uint8_t		_reserved3_[7];
89ba7cbe76Scherry };
90ba7cbe76Scherry 
91833b1484Skiyohara 
92833b1484Skiyohara /* Device Specific Structures */
93833b1484Skiyohara 
94833b1484Skiyohara struct dig64_vga_spec {
95833b1484Skiyohara 	uint8_t		num;	/*Number of Extended Address Space Descriptors*/
96833b1484Skiyohara 	struct {
97833b1484Skiyohara 		uint8_t	data[56];
98833b1484Skiyohara 	} edesc[0];
99833b1484Skiyohara } __packed;
100833b1484Skiyohara 
101833b1484Skiyohara 
102833b1484Skiyohara /* Interconnect Specific Structure */
103833b1484Skiyohara 
104833b1484Skiyohara #define DIG64_FLAGS_INTR_LEVEL		(0 << 0)	/* Level Triggered */
105833b1484Skiyohara #define DIG64_FLAGS_INTR_EDGE		(1 << 0)	/* Edge Triggered */
106833b1484Skiyohara #define DIG64_FLAGS_INTR_ACTH		(0 << 1)	/* Intr Active High */
107833b1484Skiyohara #define DIG64_FLAGS_INTR_ACTL		(1 << 1)	/* Intr Active Low */
108*1c420838Sandvar #define DIG64_FLAGS_TRANS_DENSE		(0 << 3)	/* Dense Translation */
109*1c420838Sandvar #define DIG64_FLAGS_TRANS_SPARSE	(1 << 3)	/* Sparse Translation */
110833b1484Skiyohara #define DIG64_FLAGS_TYPE_STATIC		(0 << 4)	/* Type Static */
111833b1484Skiyohara #define DIG64_FLAGS_TYPE_TRANS		(1 << 4)	/* Type Translation */
1126913cbefSandvar #define DIG64_FLAGS_INTR_SUPP		(1 << 6)	/* Interrupt supported */
113833b1484Skiyohara #define DIG64_FLAGS_MMIO_TRA_VALID	(1 << 8)
114833b1484Skiyohara #define DIG64_FLAGS_IOPORT_TRA_VALID	(1 << 9)
115833b1484Skiyohara 
116833b1484Skiyohara struct dig64_acpi_spec {
117833b1484Skiyohara 	uint8_t		type;		/* = 0 indicating ACPI */
118833b1484Skiyohara 	uint8_t		resv;		/* must be 0 */
119833b1484Skiyohara 	uint16_t	length;		/* of the ACPI Specific Structure */
120833b1484Skiyohara 	uint32_t	uid;
121833b1484Skiyohara 	uint32_t	hid;
122833b1484Skiyohara 	uint32_t	acpi_gsi;	/* ACPI Global System Interrupt */
123833b1484Skiyohara 	uint64_t	mmio_tra;
124833b1484Skiyohara 	uint64_t	ioport_tra;
125833b1484Skiyohara 	uint16_t	flags;
126833b1484Skiyohara } __packed;
127833b1484Skiyohara 
128833b1484Skiyohara struct dig64_pci_spec {
129833b1484Skiyohara 	uint8_t		type;		/* = 1 indicating PCI */
130833b1484Skiyohara 	uint8_t		resv;		/* must be 0 */
131833b1484Skiyohara 	uint16_t	length;		/* of the PCI Specific Structure */
132833b1484Skiyohara 	uint8_t		sgn;		/* PCI Segment Group Number */
133833b1484Skiyohara 	uint8_t		bus;		/* PCI Bus Number */
134833b1484Skiyohara 	uint8_t		device;		/* PCI Device Number */
135833b1484Skiyohara 	uint8_t		function;	/* PCI Function Number */
136833b1484Skiyohara 	uint16_t	device_id;
137833b1484Skiyohara 	uint16_t	vendor_id;
138833b1484Skiyohara 	uint32_t	acpi_gsi;	/* ACPI Global System Interrupt */
139833b1484Skiyohara 	uint64_t	mmio_tra;
140833b1484Skiyohara 	uint64_t	ioport_tra;
141833b1484Skiyohara 	uint16_t	flags;
142833b1484Skiyohara } __packed;
143833b1484Skiyohara 
144833b1484Skiyohara 
145833b1484Skiyohara struct dig64_pcdp_entry {
146833b1484Skiyohara 	uint8_t		type;
147833b1484Skiyohara 	uint8_t		primary;
148833b1484Skiyohara 	uint16_t	length;		/* in bytes */
149833b1484Skiyohara 	uint16_t	index;
150833b1484Skiyohara #define	DIG64_PCDP_CONOUTDEV		0
151833b1484Skiyohara #define	DIG64_PCDP_NOT_VALID		1
152833b1484Skiyohara #define	DIG64_PCDP_CONOUTDEV2		2
153833b1484Skiyohara #define	DIG64_PCDP_CONINDEV		3
154833b1484Skiyohara 
155833b1484Skiyohara 	union {
156833b1484Skiyohara 		/*
157833b1484Skiyohara 		 * Interconnect Specific Structure,
158833b1484Skiyohara 		 *   and Device Specific Structure(s)
159833b1484Skiyohara 		 */
160833b1484Skiyohara 		uint8_t	type;
161833b1484Skiyohara #define DIG64_PCDP_SPEC_ACPI		0
162833b1484Skiyohara 		struct dig64_acpi_spec acpi;
163833b1484Skiyohara #define DIG64_PCDP_SPEC_PCI		1
164833b1484Skiyohara 		struct dig64_pci_spec pci;
165833b1484Skiyohara 	} specs;
166833b1484Skiyohara } __packed;
167833b1484Skiyohara 
168ba7cbe76Scherry struct dig64_hcdp_table {
169ba7cbe76Scherry 	char		signature[4];
170ba7cbe76Scherry #define	HCDP_SIGNATURE	"HCDP"
171ba7cbe76Scherry 	uint32_t	length;
172833b1484Skiyohara 	uint8_t		revision;	/* It is PCDP, if '3' or greater. */
173ba7cbe76Scherry 	uint8_t		checksum;
174ba7cbe76Scherry 	char		oem_id[6];
175ba7cbe76Scherry 	char		oem_tbl_id[8];
176ba7cbe76Scherry 	uint32_t	oem_rev;
177ba7cbe76Scherry 	char		creator_id[4];
178ba7cbe76Scherry 	uint32_t	creator_rev;
179833b1484Skiyohara 	uint32_t	entries;	/* Number of Type0 and Type1 Entries. */
180833b1484Skiyohara 	union dev_desc {	/* Device Descriptor */
181833b1484Skiyohara 		uint8_t type;
182833b1484Skiyohara #define	DIG64_ENTRYTYPE_TYPE0		0	/* (UART | Bidirect) */
183833b1484Skiyohara #define	DIG64_ENTRYTYPE_TYPE1		1	/* (UART | Debug Port) */
184833b1484Skiyohara #define	DIG64_ENTRYTYPE_BIDIRECT	(0<<0)	/* bidirectional console */
185833b1484Skiyohara #define	DIG64_ENTRYTYPE_DEBUGPORT	(1<<0)	/* debug port */
186833b1484Skiyohara #define	DIG64_ENTRYTYPE_OUTONLY		(2<<0)	/* console output-only */
187833b1484Skiyohara #define	DIG64_ENTRYTYPE_INONLY		(3<<0)	/* console input-only */
188833b1484Skiyohara #define	DIG64_ENTRYTYPE_UART		(0<<3)
189833b1484Skiyohara #define	DIG64_ENTRYTYPE_VGA		(1<<3)
190833b1484Skiyohara #define	DIG64_ENTRYTYPE_VENDOR		(1<<7)	/* Vendor specific */
191833b1484Skiyohara 		struct dig64_hcdp_entry uart;
192833b1484Skiyohara 		struct dig64_pcdp_entry pcdp;
193833b1484Skiyohara 	} entry[0];
194ba7cbe76Scherry };
195ba7cbe76Scherry 
196ba7cbe76Scherry #endif
197