1 /* $NetBSD: disasm_decode.c,v 1.1 2006/04/07 14:21:18 cherry Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* __FBSDID("$FreeBSD: src/sys/ia64/disasm/disasm_decode.c,v 1.3 2005/01/06 22:18:22 imp Exp $"); */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <ia64/disasm/disasm_int.h> 36 #include <ia64/disasm/disasm.h> 37 38 /* 39 * Template names. 40 */ 41 static const char *asm_templname[] = { 42 "MII", "MII;", "MI;I", "MI;I;", "MLX", "MLX;", 0, 0, 43 "MMI", "MMI;", "M;MI", "M;MI;", "MFI", "MFI;", "MMF", "MMF;", 44 "MIB", "MIB;", "MBB", "MBB;", 0, 0, "BBB", "BBB;", 45 "MMB", "MMB;", 0, 0, "MFB", "MFB;", 0, 0 46 }; 47 48 /* 49 * Decode A-unit instructions. 50 */ 51 static int 52 asm_decodeA(uint64_t bits, struct asm_bundle *b, int slot) 53 { 54 enum asm_fmt fmt; 55 enum asm_op op; 56 57 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 58 switch((int)OPCODE(bits)) { 59 case 0x8: 60 switch (FIELD(bits, 34, 2)) { /* x2a */ 61 case 0x0: 62 if (FIELD(bits, 33, 1) == 0) { /* ve */ 63 switch (FIELD(bits, 29, 4)) { /* x4 */ 64 case 0x0: 65 if (FIELD(bits, 27, 2) <= 1) /* x2b */ 66 op = ASM_OP_ADD, 67 fmt = ASM_FMT_A1; 68 break; 69 case 0x1: 70 if (FIELD(bits, 27, 2) <= 1) /* x2b */ 71 op = ASM_OP_SUB, 72 fmt = ASM_FMT_A1; 73 break; 74 case 0x2: 75 if (FIELD(bits, 27, 2) == 0) /* x2b */ 76 op = ASM_OP_ADDP4, 77 fmt = ASM_FMT_A1; 78 break; 79 case 0x3: 80 switch (FIELD(bits, 27, 2)) { /* x2b */ 81 case 0x0: 82 op = ASM_OP_AND, 83 fmt = ASM_FMT_A1; 84 break; 85 case 0x1: 86 op = ASM_OP_ANDCM, 87 fmt = ASM_FMT_A1; 88 break; 89 case 0x2: 90 op = ASM_OP_OR, 91 fmt = ASM_FMT_A1; 92 break; 93 case 0x3: 94 op = ASM_OP_XOR, 95 fmt = ASM_FMT_A1; 96 break; 97 } 98 break; 99 case 0xB: 100 switch (FIELD(bits, 27, 2)) { /* x2b */ 101 case 0x0: 102 op = ASM_OP_AND, 103 fmt = ASM_FMT_A3; 104 break; 105 case 0x1: 106 op = ASM_OP_ANDCM, 107 fmt = ASM_FMT_A3; 108 break; 109 case 0x2: 110 op = ASM_OP_OR, 111 fmt = ASM_FMT_A3; 112 break; 113 case 0x3: 114 op = ASM_OP_XOR, 115 fmt = ASM_FMT_A3; 116 break; 117 } 118 break; 119 case 0x4: 120 op = ASM_OP_SHLADD, fmt = ASM_FMT_A2; 121 break; 122 case 0x6: 123 op = ASM_OP_SHLADDP4, fmt = ASM_FMT_A2; 124 break; 125 case 0x9: 126 if (FIELD(bits, 27, 2) == 1) /* x2b */ 127 op = ASM_OP_SUB, 128 fmt = ASM_FMT_A3; 129 break; 130 } 131 } 132 break; 133 case 0x1: 134 switch (FIELD(bits, 29, 8)) { /* za + x2a + zb + x4 */ 135 case 0x20: 136 switch (FIELD(bits, 27, 2)) { /* x2b */ 137 case 0x0: 138 op = ASM_OP_PADD1_, fmt = ASM_FMT_A9; 139 break; 140 case 0x1: 141 op = ASM_OP_PADD1_SSS, 142 fmt = ASM_FMT_A9; 143 break; 144 case 0x2: 145 op = ASM_OP_PADD1_UUU, 146 fmt = ASM_FMT_A9; 147 break; 148 case 0x3: 149 op = ASM_OP_PADD1_UUS, 150 fmt = ASM_FMT_A9; 151 break; 152 } 153 break; 154 case 0x21: 155 switch (FIELD(bits, 27, 2)) { /* x2b */ 156 case 0x0: 157 op = ASM_OP_PSUB1_, fmt = ASM_FMT_A9; 158 break; 159 case 0x1: 160 op = ASM_OP_PSUB1_SSS, 161 fmt = ASM_FMT_A9; 162 break; 163 case 0x2: 164 op = ASM_OP_PSUB1_UUU, 165 fmt = ASM_FMT_A9; 166 break; 167 case 0x3: 168 op = ASM_OP_PSUB1_UUS, 169 fmt = ASM_FMT_A9; 170 break; 171 } 172 break; 173 case 0x22: 174 switch (FIELD(bits, 27, 2)) { /* x2b */ 175 case 0x2: 176 op = ASM_OP_PAVG1_, fmt = ASM_FMT_A9; 177 break; 178 case 0x3: 179 op = ASM_OP_PAVG1_RAZ, 180 fmt = ASM_FMT_A9; 181 break; 182 } 183 break; 184 case 0x23: 185 if (FIELD(bits, 27, 2) == 2) /* x2b */ 186 op = ASM_OP_PAVGSUB1, fmt = ASM_FMT_A9; 187 break; 188 case 0x29: 189 switch (FIELD(bits, 27, 2)) { /* x2b */ 190 case 0x0: 191 op = ASM_OP_PCMP1_EQ, fmt = ASM_FMT_A9; 192 break; 193 case 0x1: 194 op = ASM_OP_PCMP1_GT, fmt = ASM_FMT_A9; 195 break; 196 } 197 break; 198 case 0x30: 199 switch (FIELD(bits, 27, 2)) { /* x2b */ 200 case 0x0: 201 op = ASM_OP_PADD2_, fmt = ASM_FMT_A9; 202 break; 203 case 0x1: 204 op = ASM_OP_PADD2_SSS, 205 fmt = ASM_FMT_A9; 206 break; 207 case 0x2: 208 op = ASM_OP_PADD2_UUU, 209 fmt = ASM_FMT_A9; 210 break; 211 case 0x3: 212 op = ASM_OP_PADD2_UUS, 213 fmt = ASM_FMT_A9; 214 break; 215 } 216 break; 217 case 0x31: 218 switch (FIELD(bits, 27, 2)) { /* x2b */ 219 case 0x0: 220 op = ASM_OP_PSUB2_, fmt = ASM_FMT_A9; 221 break; 222 case 0x1: 223 op = ASM_OP_PSUB2_SSS, 224 fmt = ASM_FMT_A9; 225 break; 226 case 0x2: 227 op = ASM_OP_PSUB2_UUU, 228 fmt = ASM_FMT_A9; 229 break; 230 case 0x3: 231 op = ASM_OP_PSUB2_UUS, 232 fmt = ASM_FMT_A9; 233 break; 234 } 235 break; 236 case 0x32: 237 switch (FIELD(bits, 27, 2)) { /* x2b */ 238 case 0x2: 239 op = ASM_OP_PAVG2_, fmt = ASM_FMT_A9; 240 break; 241 case 0x3: 242 op = ASM_OP_PAVG2_RAZ, 243 fmt = ASM_FMT_A9; 244 break; 245 } 246 break; 247 case 0x33: 248 if (FIELD(bits, 27, 2) == 2) /* x2b */ 249 op = ASM_OP_PAVGSUB2, fmt = ASM_FMT_A9; 250 break; 251 case 0x34: 252 op = ASM_OP_PSHLADD2, fmt = ASM_FMT_A10; 253 break; 254 case 0x36: 255 op = ASM_OP_PSHRADD2, fmt = ASM_FMT_A10; 256 break; 257 case 0x39: 258 switch (FIELD(bits, 27, 2)) { /* x2b */ 259 case 0x0: 260 op = ASM_OP_PCMP2_EQ, fmt = ASM_FMT_A9; 261 break; 262 case 0x1: 263 op = ASM_OP_PCMP2_GT, fmt = ASM_FMT_A9; 264 break; 265 } 266 break; 267 case 0xA0: 268 if (FIELD(bits, 27, 2) == 0) /* x2b */ 269 op = ASM_OP_PADD4, fmt = ASM_FMT_A9; 270 break; 271 case 0xA1: 272 if (FIELD(bits, 27, 2) == 0) /* x2b */ 273 op = ASM_OP_PSUB4, fmt = ASM_FMT_A9; 274 break; 275 case 0xA9: 276 switch (FIELD(bits, 27, 2)) { /* x2b */ 277 case 0x0: 278 op = ASM_OP_PCMP4_EQ, fmt = ASM_FMT_A9; 279 break; 280 case 0x1: 281 op = ASM_OP_PCMP4_GT, fmt = ASM_FMT_A9; 282 break; 283 } 284 break; 285 } 286 break; 287 case 0x2: 288 if (FIELD(bits, 33, 1) == 0) /* ve */ 289 op = ASM_OP_ADDS, fmt = ASM_FMT_A4; 290 break; 291 case 0x3: 292 if (FIELD(bits, 33, 1) == 0) /* ve */ 293 op = ASM_OP_ADDP4, fmt = ASM_FMT_A4; 294 break; 295 } 296 break; 297 case 0x9: 298 op = ASM_OP_ADDL, fmt = ASM_FMT_A5; 299 break; 300 case 0xC: case 0xD: case 0xE: 301 if (FIELD(bits, 12, 1) == 0) { /* c */ 302 switch (FIELD(bits, 33, 8)) { /* maj + tb + x2 + ta */ 303 case 0xC0: 304 op = ASM_OP_CMP_LT, fmt = ASM_FMT_A6; 305 break; 306 case 0xC1: 307 op = ASM_OP_CMP_EQ_AND, fmt = ASM_FMT_A6; 308 break; 309 case 0xC2: 310 op = ASM_OP_CMP4_LT, fmt = ASM_FMT_A6; 311 break; 312 case 0xC3: 313 op = ASM_OP_CMP4_EQ_AND, fmt = ASM_FMT_A6; 314 break; 315 case 0xC4: case 0xCC: 316 op = ASM_OP_CMP_LT, fmt = ASM_FMT_A8; 317 break; 318 case 0xC5: case 0xCD: 319 op = ASM_OP_CMP_EQ_AND, fmt = ASM_FMT_A8; 320 break; 321 case 0xC6: case 0xCE: 322 op = ASM_OP_CMP4_LT, fmt = ASM_FMT_A8; 323 break; 324 case 0xC7: case 0xCF: 325 op = ASM_OP_CMP4_EQ_AND, fmt = ASM_FMT_A8; 326 break; 327 case 0xC8: 328 op = ASM_OP_CMP_GT_AND, fmt = ASM_FMT_A7; 329 break; 330 case 0xC9: 331 op = ASM_OP_CMP_GE_AND, fmt = ASM_FMT_A7; 332 break; 333 case 0xCA: 334 op = ASM_OP_CMP4_GT_AND, fmt = ASM_FMT_A7; 335 break; 336 case 0xCB: 337 op = ASM_OP_CMP4_GE_AND, fmt = ASM_FMT_A7; 338 break; 339 case 0xD0: 340 op = ASM_OP_CMP_LTU, fmt = ASM_FMT_A6; 341 break; 342 case 0xD1: 343 op = ASM_OP_CMP_EQ_OR, fmt = ASM_FMT_A6; 344 break; 345 case 0xD2: 346 op = ASM_OP_CMP4_LTU, fmt = ASM_FMT_A6; 347 break; 348 case 0xD3: 349 op = ASM_OP_CMP4_EQ_OR, fmt = ASM_FMT_A6; 350 break; 351 case 0xD4: case 0xDC: 352 op = ASM_OP_CMP_LTU, fmt = ASM_FMT_A8; 353 break; 354 case 0xD5: case 0xDD: 355 op = ASM_OP_CMP_EQ_OR, fmt = ASM_FMT_A8; 356 break; 357 case 0xD6: case 0xDE: 358 op = ASM_OP_CMP4_LTU, fmt = ASM_FMT_A8; 359 break; 360 case 0xD7: case 0xDF: 361 op = ASM_OP_CMP4_EQ_OR, fmt = ASM_FMT_A8; 362 break; 363 case 0xD8: 364 op = ASM_OP_CMP_GT_OR, fmt = ASM_FMT_A7; 365 break; 366 case 0xD9: 367 op = ASM_OP_CMP_GE_OR, fmt = ASM_FMT_A7; 368 break; 369 case 0xDA: 370 op = ASM_OP_CMP4_GT_OR, fmt = ASM_FMT_A7; 371 break; 372 case 0xDB: 373 op = ASM_OP_CMP4_GE_OR, fmt = ASM_FMT_A7; 374 break; 375 case 0xE0: 376 op = ASM_OP_CMP_EQ, fmt = ASM_FMT_A6; 377 break; 378 case 0xE1: 379 op = ASM_OP_CMP_EQ_OR_ANDCM, fmt = ASM_FMT_A6; 380 break; 381 case 0xE2: 382 op = ASM_OP_CMP4_EQ, fmt = ASM_FMT_A6; 383 break; 384 case 0xE3: 385 op = ASM_OP_CMP4_EQ_OR_ANDCM, fmt = ASM_FMT_A6; 386 break; 387 case 0xE4: case 0xEC: 388 op = ASM_OP_CMP_EQ, fmt = ASM_FMT_A8; 389 break; 390 case 0xE5: case 0xED: 391 op = ASM_OP_CMP_EQ_OR_ANDCM, fmt = ASM_FMT_A8; 392 break; 393 case 0xE6: case 0xEE: 394 op = ASM_OP_CMP4_EQ, fmt = ASM_FMT_A8; 395 break; 396 case 0xE7: case 0xEF: 397 op = ASM_OP_CMP4_EQ_OR_ANDCM, fmt = ASM_FMT_A8; 398 break; 399 case 0xE8: 400 op = ASM_OP_CMP_GT_OR_ANDCM, fmt = ASM_FMT_A7; 401 break; 402 case 0xE9: 403 op = ASM_OP_CMP_GE_OR_ANDCM, fmt = ASM_FMT_A7; 404 break; 405 case 0xEA: 406 op = ASM_OP_CMP4_GT_OR_ANDCM, fmt = ASM_FMT_A7; 407 break; 408 case 0xEB: 409 op = ASM_OP_CMP4_GE_OR_ANDCM, fmt = ASM_FMT_A7; 410 break; 411 } 412 } else { 413 switch (FIELD(bits, 33, 8)) { /* maj + tb + x2 + ta */ 414 case 0xC0: 415 op = ASM_OP_CMP_LT_UNC, fmt = ASM_FMT_A6; 416 break; 417 case 0xC1: 418 op = ASM_OP_CMP_NE_AND, fmt = ASM_FMT_A6; 419 break; 420 case 0xC2: 421 op = ASM_OP_CMP4_LT_UNC, fmt = ASM_FMT_A6; 422 break; 423 case 0xC3: 424 op = ASM_OP_CMP4_NE_AND, fmt = ASM_FMT_A6; 425 break; 426 case 0xC4: case 0xCC: 427 op = ASM_OP_CMP_LT_UNC, fmt = ASM_FMT_A8; 428 break; 429 case 0xC5: case 0xCD: 430 op = ASM_OP_CMP_NE_AND, fmt = ASM_FMT_A8; 431 break; 432 case 0xC6: case 0xCE: 433 op = ASM_OP_CMP4_LT_UNC, fmt = ASM_FMT_A8; 434 break; 435 case 0xC7: case 0xCF: 436 op = ASM_OP_CMP4_NE_AND, fmt = ASM_FMT_A8; 437 break; 438 case 0xC8: 439 op = ASM_OP_CMP_LE_AND, fmt = ASM_FMT_A7; 440 break; 441 case 0xC9: 442 op = ASM_OP_CMP_LT_AND, fmt = ASM_FMT_A7; 443 break; 444 case 0xCA: 445 op = ASM_OP_CMP4_LE_AND, fmt = ASM_FMT_A7; 446 break; 447 case 0xCB: 448 op = ASM_OP_CMP4_LT_AND, fmt = ASM_FMT_A7; 449 break; 450 case 0xD0: 451 op = ASM_OP_CMP_LTU_UNC, fmt = ASM_FMT_A6; 452 break; 453 case 0xD1: 454 op = ASM_OP_CMP_NE_OR, fmt = ASM_FMT_A6; 455 break; 456 case 0xD2: 457 op = ASM_OP_CMP4_LTU_UNC, fmt = ASM_FMT_A6; 458 break; 459 case 0xD3: 460 op = ASM_OP_CMP4_NE_OR, fmt = ASM_FMT_A6; 461 break; 462 case 0xD4: case 0xDC: 463 op = ASM_OP_CMP_LTU_UNC, fmt = ASM_FMT_A8; 464 break; 465 case 0xD5: case 0xDD: 466 op = ASM_OP_CMP_NE_OR, fmt = ASM_FMT_A8; 467 break; 468 case 0xD6: case 0xDE: 469 op = ASM_OP_CMP4_LTU_UNC, fmt = ASM_FMT_A8; 470 break; 471 case 0xD7: case 0xDF: 472 op = ASM_OP_CMP4_NE_OR, fmt = ASM_FMT_A8; 473 break; 474 case 0xD8: 475 op = ASM_OP_CMP_LE_OR, fmt = ASM_FMT_A7; 476 break; 477 case 0xD9: 478 op = ASM_OP_CMP_LT_OR, fmt = ASM_FMT_A7; 479 break; 480 case 0xDA: 481 op = ASM_OP_CMP4_LE_OR, fmt = ASM_FMT_A7; 482 break; 483 case 0xDB: 484 op = ASM_OP_CMP4_LT_OR, fmt = ASM_FMT_A7; 485 break; 486 case 0xE0: 487 op = ASM_OP_CMP_EQ_UNC, fmt = ASM_FMT_A6; 488 break; 489 case 0xE1: 490 op = ASM_OP_CMP_NE_OR_ANDCM, fmt = ASM_FMT_A6; 491 break; 492 case 0xE2: 493 op = ASM_OP_CMP4_EQ_UNC, fmt = ASM_FMT_A6; 494 break; 495 case 0xE3: 496 op = ASM_OP_CMP4_NE_OR_ANDCM, fmt = ASM_FMT_A6; 497 break; 498 case 0xE4: case 0xEC: 499 op = ASM_OP_CMP_EQ_UNC, fmt = ASM_FMT_A8; 500 break; 501 case 0xE5: case 0xED: 502 op = ASM_OP_CMP_NE_OR_ANDCM, fmt = ASM_FMT_A8; 503 break; 504 case 0xE6: case 0xEE: 505 op = ASM_OP_CMP4_EQ_UNC, fmt = ASM_FMT_A8; 506 break; 507 case 0xE7: case 0xEF: 508 op = ASM_OP_CMP4_NE_OR_ANDCM, fmt = ASM_FMT_A8; 509 break; 510 case 0xE8: 511 op = ASM_OP_CMP_LE_OR_ANDCM, fmt = ASM_FMT_A7; 512 break; 513 case 0xE9: 514 op = ASM_OP_CMP_LT_OR_ANDCM, fmt = ASM_FMT_A7; 515 break; 516 case 0xEA: 517 op = ASM_OP_CMP4_LE_OR_ANDCM, fmt = ASM_FMT_A7; 518 break; 519 case 0xEB: 520 op = ASM_OP_CMP4_LT_OR_ANDCM, fmt = ASM_FMT_A7; 521 break; 522 } 523 } 524 break; 525 } 526 527 if (op != ASM_OP_NONE) 528 return (asm_extract(op, fmt, bits, b, slot)); 529 return (0); 530 } 531 532 /* 533 * Decode B-unit instructions. 534 */ 535 static int 536 asm_decodeB(uint64_t ip, struct asm_bundle *b, int slot) 537 { 538 uint64_t bits; 539 enum asm_fmt fmt; 540 enum asm_op op; 541 542 bits = SLOT(ip, slot); 543 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 544 545 switch((int)OPCODE(bits)) { 546 case 0x0: 547 switch (FIELD(bits, 27, 6)) { /* x6 */ 548 case 0x0: 549 op = ASM_OP_BREAK_B, fmt = ASM_FMT_B9; 550 break; 551 case 0x2: 552 op = ASM_OP_COVER, fmt = ASM_FMT_B8; 553 break; 554 case 0x4: 555 op = ASM_OP_CLRRRB_, fmt = ASM_FMT_B8; 556 break; 557 case 0x5: 558 op = ASM_OP_CLRRRB_PR, fmt = ASM_FMT_B8; 559 break; 560 case 0x8: 561 op = ASM_OP_RFI, fmt = ASM_FMT_B8; 562 break; 563 case 0xC: 564 op = ASM_OP_BSW_0, fmt = ASM_FMT_B8; 565 break; 566 case 0xD: 567 op = ASM_OP_BSW_1, fmt = ASM_FMT_B8; 568 break; 569 case 0x10: 570 op = ASM_OP_EPC, fmt = ASM_FMT_B8; 571 break; 572 case 0x20: 573 switch (FIELD(bits, 6, 3)) { /* btype */ 574 case 0x0: 575 op = ASM_OP_BR_COND, fmt = ASM_FMT_B4; 576 break; 577 case 0x1: 578 op = ASM_OP_BR_IA, fmt = ASM_FMT_B4; 579 break; 580 } 581 break; 582 case 0x21: 583 if (FIELD(bits, 6, 3) == 4) /* btype */ 584 op = ASM_OP_BR_RET, fmt = ASM_FMT_B4; 585 break; 586 } 587 break; 588 case 0x1: 589 op = ASM_OP_BR_CALL, fmt = ASM_FMT_B5; 590 break; 591 case 0x2: 592 switch (FIELD(bits, 27, 6)) { /* x6 */ 593 case 0x0: 594 op = ASM_OP_NOP_B, fmt = ASM_FMT_B9; 595 break; 596 case 0x10: 597 op = ASM_OP_BRP_, fmt = ASM_FMT_B7; 598 break; 599 case 0x11: 600 op = ASM_OP_BRP_RET, fmt = ASM_FMT_B7; 601 break; 602 } 603 break; 604 case 0x4: 605 switch (FIELD(bits, 6, 3)) { /* btype */ 606 case 0x0: 607 op = ASM_OP_BR_COND, fmt = ASM_FMT_B1; 608 break; 609 case 0x2: 610 op = ASM_OP_BR_WEXIT, fmt = ASM_FMT_B1; 611 break; 612 case 0x3: 613 op = ASM_OP_BR_WTOP, fmt = ASM_FMT_B1; 614 break; 615 case 0x5: 616 op = ASM_OP_BR_CLOOP, fmt = ASM_FMT_B2; 617 break; 618 case 0x6: 619 op = ASM_OP_BR_CEXIT, fmt = ASM_FMT_B2; 620 break; 621 case 0x7: 622 op = ASM_OP_BR_CTOP, fmt = ASM_FMT_B2; 623 break; 624 } 625 break; 626 case 0x5: 627 op = ASM_OP_BR_CALL, fmt = ASM_FMT_B3; 628 break; 629 case 0x7: 630 op = ASM_OP_BRP_, fmt = ASM_FMT_B6; 631 break; 632 } 633 634 if (op != ASM_OP_NONE) 635 return (asm_extract(op, fmt, bits, b, slot)); 636 return (0); 637 } 638 639 /* 640 * Decode F-unit instructions. 641 */ 642 static int 643 asm_decodeF(uint64_t ip, struct asm_bundle *b, int slot) 644 { 645 uint64_t bits; 646 enum asm_fmt fmt; 647 enum asm_op op; 648 649 bits = SLOT(ip, slot); 650 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 651 652 switch((int)OPCODE(bits)) { 653 case 0x0: 654 if (FIELD(bits, 33, 1) == 0) { /* x */ 655 switch (FIELD(bits, 27, 6)) { /* x6 */ 656 case 0x0: 657 op = ASM_OP_BREAK_F, fmt = ASM_FMT_F15; 658 break; 659 case 0x1: 660 op = ASM_OP_NOP_F, fmt = ASM_FMT_F15; 661 break; 662 case 0x4: 663 op = ASM_OP_FSETC, fmt = ASM_FMT_F12; 664 break; 665 case 0x5: 666 op = ASM_OP_FCLRF, fmt = ASM_FMT_F13; 667 break; 668 case 0x8: 669 op = ASM_OP_FCHKF, fmt = ASM_FMT_F14; 670 break; 671 case 0x10: 672 op = ASM_OP_FMERGE_S, fmt = ASM_FMT_F9; 673 break; 674 case 0x11: 675 op = ASM_OP_FMERGE_NS, fmt = ASM_FMT_F9; 676 break; 677 case 0x12: 678 op = ASM_OP_FMERGE_SE, fmt = ASM_FMT_F9; 679 break; 680 case 0x14: 681 op = ASM_OP_FMIN, fmt = ASM_FMT_F8; 682 break; 683 case 0x15: 684 op = ASM_OP_FMAX, fmt = ASM_FMT_F8; 685 break; 686 case 0x16: 687 op = ASM_OP_FAMIN, fmt = ASM_FMT_F8; 688 break; 689 case 0x17: 690 op = ASM_OP_FAMAX, fmt = ASM_FMT_F8; 691 break; 692 case 0x18: 693 op = ASM_OP_FCVT_FX, fmt = ASM_FMT_F10; 694 break; 695 case 0x19: 696 op = ASM_OP_FCVT_FXU, fmt = ASM_FMT_F10; 697 break; 698 case 0x1A: 699 op = ASM_OP_FCVT_FX_TRUNC, fmt = ASM_FMT_F10; 700 break; 701 case 0x1B: 702 op = ASM_OP_FCVT_FXU_TRUNC, fmt = ASM_FMT_F10; 703 break; 704 case 0x1C: 705 op = ASM_OP_FCVT_XF, fmt = ASM_FMT_F11; 706 break; 707 case 0x28: 708 op = ASM_OP_FPACK, fmt = ASM_FMT_F9; 709 break; 710 case 0x2C: 711 op = ASM_OP_FAND, fmt = ASM_FMT_F9; 712 break; 713 case 0x2D: 714 op = ASM_OP_FANDCM, fmt = ASM_FMT_F9; 715 break; 716 case 0x2E: 717 op = ASM_OP_FOR, fmt = ASM_FMT_F9; 718 break; 719 case 0x2F: 720 op = ASM_OP_FXOR, fmt = ASM_FMT_F9; 721 break; 722 case 0x34: 723 op = ASM_OP_FSWAP_, fmt = ASM_FMT_F9; 724 break; 725 case 0x35: 726 op = ASM_OP_FSWAP_NL, fmt = ASM_FMT_F9; 727 break; 728 case 0x36: 729 op = ASM_OP_FSWAP_NR, fmt = ASM_FMT_F9; 730 break; 731 case 0x39: 732 op = ASM_OP_FMIX_LR, fmt = ASM_FMT_F9; 733 break; 734 case 0x3A: 735 op = ASM_OP_FMIX_R, fmt = ASM_FMT_F9; 736 break; 737 case 0x3B: 738 op = ASM_OP_FMIX_L, fmt = ASM_FMT_F9; 739 break; 740 case 0x3C: 741 op = ASM_OP_FSXT_R, fmt = ASM_FMT_F9; 742 break; 743 case 0x3D: 744 op = ASM_OP_FSXT_L, fmt = ASM_FMT_F9; 745 break; 746 } 747 } else { 748 if (FIELD(bits, 36, 1) == 0) /* q */ 749 op = ASM_OP_FRCPA, fmt = ASM_FMT_F6; 750 else 751 op = ASM_OP_FRSQRTA, fmt = ASM_FMT_F7; 752 } 753 break; 754 case 0x1: 755 if (FIELD(bits, 33, 1) == 0) { /* x */ 756 switch (FIELD(bits, 27, 6)) { /* x6 */ 757 case 0x10: 758 op = ASM_OP_FPMERGE_S, fmt = ASM_FMT_F9; 759 break; 760 case 0x11: 761 op = ASM_OP_FPMERGE_NS, fmt = ASM_FMT_F9; 762 break; 763 case 0x12: 764 op = ASM_OP_FPMERGE_SE, fmt = ASM_FMT_F9; 765 break; 766 case 0x14: 767 op = ASM_OP_FPMIN, fmt = ASM_FMT_F8; 768 break; 769 case 0x15: 770 op = ASM_OP_FPMAX, fmt = ASM_FMT_F8; 771 break; 772 case 0x16: 773 op = ASM_OP_FPAMIN, fmt = ASM_FMT_F8; 774 break; 775 case 0x17: 776 op = ASM_OP_FPAMAX, fmt = ASM_FMT_F8; 777 break; 778 case 0x18: 779 op = ASM_OP_FPCVT_FX, fmt = ASM_FMT_F10; 780 break; 781 case 0x19: 782 op = ASM_OP_FPCVT_FXU, fmt = ASM_FMT_F10; 783 break; 784 case 0x1A: 785 op = ASM_OP_FPCVT_FX_TRUNC, fmt = ASM_FMT_F10; 786 break; 787 case 0x1B: 788 op = ASM_OP_FPCVT_FXU_TRUNC, fmt = ASM_FMT_F10; 789 break; 790 case 0x30: 791 op = ASM_OP_FPCMP_EQ, fmt = ASM_FMT_F8; 792 break; 793 case 0x31: 794 op = ASM_OP_FPCMP_LT, fmt = ASM_FMT_F8; 795 break; 796 case 0x32: 797 op = ASM_OP_FPCMP_LE, fmt = ASM_FMT_F8; 798 break; 799 case 0x33: 800 op = ASM_OP_FPCMP_UNORD, fmt = ASM_FMT_F8; 801 break; 802 case 0x34: 803 op = ASM_OP_FPCMP_NEQ, fmt = ASM_FMT_F8; 804 break; 805 case 0x35: 806 op = ASM_OP_FPCMP_NLT, fmt = ASM_FMT_F8; 807 break; 808 case 0x36: 809 op = ASM_OP_FPCMP_NLE, fmt = ASM_FMT_F8; 810 break; 811 case 0x37: 812 op = ASM_OP_FPCMP_ORD, fmt = ASM_FMT_F8; 813 break; 814 } 815 } else { 816 if (FIELD(bits, 36, 1) == 0) /* q */ 817 op = ASM_OP_FPRCPA, fmt = ASM_FMT_F6; 818 else 819 op = ASM_OP_FPRSQRTA, fmt = ASM_FMT_F7; 820 } 821 break; 822 case 0x4: 823 op = ASM_OP_FCMP, fmt = ASM_FMT_F4; 824 break; 825 case 0x5: 826 op = ASM_OP_FCLASS_M, fmt = ASM_FMT_F5; 827 break; 828 case 0x8: 829 if (FIELD(bits, 36, 1) == 0) /* x */ 830 op = ASM_OP_FMA_, fmt = ASM_FMT_F1; 831 else 832 op = ASM_OP_FMA_S, fmt = ASM_FMT_F1; 833 break; 834 case 0x9: 835 if (FIELD(bits, 36, 1) == 0) /* x */ 836 op = ASM_OP_FMA_D, fmt = ASM_FMT_F1; 837 else 838 op = ASM_OP_FPMA, fmt = ASM_FMT_F1; 839 break; 840 case 0xA: 841 if (FIELD(bits, 36, 1) == 0) /* x */ 842 op = ASM_OP_FMS_, fmt = ASM_FMT_F1; 843 else 844 op = ASM_OP_FMS_S, fmt = ASM_FMT_F1; 845 break; 846 case 0xB: 847 if (FIELD(bits, 36, 1) == 0) /* x */ 848 op = ASM_OP_FMS_D, fmt = ASM_FMT_F1; 849 else 850 op = ASM_OP_FPMS, fmt = ASM_FMT_F1; 851 break; 852 case 0xC: 853 if (FIELD(bits, 36, 1) == 0) /* x */ 854 op = ASM_OP_FNMA_, fmt = ASM_FMT_F1; 855 else 856 op = ASM_OP_FNMA_S, fmt = ASM_FMT_F1; 857 break; 858 case 0xD: 859 if (FIELD(bits, 36, 1) == 0) /* x */ 860 op = ASM_OP_FNMA_D, fmt = ASM_FMT_F1; 861 else 862 op = ASM_OP_FPNMA, fmt = ASM_FMT_F1; 863 break; 864 case 0xE: 865 if (FIELD(bits, 36, 1) == 1) { /* x */ 866 switch (FIELD(bits, 34, 2)) { /* x2 */ 867 case 0x0: 868 op = ASM_OP_XMA_L, fmt = ASM_FMT_F2; 869 break; 870 case 0x2: 871 op = ASM_OP_XMA_HU, fmt = ASM_FMT_F2; 872 break; 873 case 0x3: 874 op = ASM_OP_XMA_H, fmt = ASM_FMT_F2; 875 break; 876 } 877 } else 878 op = ASM_OP_FSELECT, fmt = ASM_FMT_F3; 879 break; 880 } 881 882 if (op != ASM_OP_NONE) 883 return (asm_extract(op, fmt, bits, b, slot)); 884 return (0); 885 } 886 887 /* 888 * Decode I-unit instructions. 889 */ 890 static int 891 asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot) 892 { 893 uint64_t bits; 894 enum asm_fmt fmt; 895 enum asm_op op; 896 897 bits = SLOT(ip, slot); 898 if ((int)OPCODE(bits) >= 8) 899 return (asm_decodeA(bits, b, slot)); 900 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 901 902 switch((int)OPCODE(bits)) { 903 case 0x0: 904 switch (FIELD(bits, 33, 3)) { /* x3 */ 905 case 0x0: 906 switch (FIELD(bits, 27, 6)) { /* x6 */ 907 case 0x0: 908 op = ASM_OP_BREAK_I, fmt = ASM_FMT_I19; 909 break; 910 case 0x1: 911 op = ASM_OP_NOP_I, fmt = ASM_FMT_I19; 912 break; 913 case 0xA: 914 op = ASM_OP_MOV_I, fmt = ASM_FMT_I27; 915 break; 916 case 0x10: 917 op = ASM_OP_ZXT1, fmt = ASM_FMT_I29; 918 break; 919 case 0x11: 920 op = ASM_OP_ZXT2, fmt = ASM_FMT_I29; 921 break; 922 case 0x12: 923 op = ASM_OP_ZXT4, fmt = ASM_FMT_I29; 924 break; 925 case 0x14: 926 op = ASM_OP_SXT1, fmt = ASM_FMT_I29; 927 break; 928 case 0x15: 929 op = ASM_OP_SXT2, fmt = ASM_FMT_I29; 930 break; 931 case 0x16: 932 op = ASM_OP_SXT4, fmt = ASM_FMT_I29; 933 break; 934 case 0x18: 935 op = ASM_OP_CZX1_L, fmt = ASM_FMT_I29; 936 break; 937 case 0x19: 938 op = ASM_OP_CZX2_L, fmt = ASM_FMT_I29; 939 break; 940 case 0x1C: 941 op = ASM_OP_CZX1_R, fmt = ASM_FMT_I29; 942 break; 943 case 0x1D: 944 op = ASM_OP_CZX2_R, fmt = ASM_FMT_I29; 945 break; 946 case 0x2A: 947 op = ASM_OP_MOV_I, fmt = ASM_FMT_I26; 948 break; 949 case 0x30: 950 op = ASM_OP_MOV_IP, fmt = ASM_FMT_I25; 951 break; 952 case 0x31: 953 op = ASM_OP_MOV_, fmt = ASM_FMT_I22; 954 break; 955 case 0x32: 956 op = ASM_OP_MOV_I, fmt = ASM_FMT_I28; 957 break; 958 case 0x33: 959 op = ASM_OP_MOV_PR, fmt = ASM_FMT_I25; 960 break; 961 } 962 break; 963 case 0x1: 964 op = ASM_OP_CHK_S_I, fmt = ASM_FMT_I20; 965 break; 966 case 0x2: 967 op = ASM_OP_MOV_, fmt = ASM_FMT_I24; 968 break; 969 case 0x3: 970 op = ASM_OP_MOV_, fmt = ASM_FMT_I23; 971 break; 972 case 0x7: 973 if (FIELD(bits, 22, 1) == 0) /* x */ 974 op = ASM_OP_MOV_, fmt = ASM_FMT_I21; 975 else 976 op = ASM_OP_MOV_RET, fmt = ASM_FMT_I21; 977 break; 978 } 979 break; 980 case 0x4: 981 op = ASM_OP_DEP_, fmt = ASM_FMT_I15; 982 break; 983 case 0x5: 984 switch (FIELD(bits, 33, 3)) { /* x + x2 */ 985 case 0x0: 986 if (FIELD(bits, 36, 1) == 0) { /* tb */ 987 switch (FIELD(bits, 12, 2)) { /* c + y */ 988 case 0x0: 989 op = ASM_OP_TBIT_Z, fmt = ASM_FMT_I16; 990 break; 991 case 0x1: 992 op = ASM_OP_TBIT_Z_UNC, 993 fmt = ASM_FMT_I16; 994 break; 995 case 0x2: 996 op = ASM_OP_TNAT_Z, fmt = ASM_FMT_I17; 997 break; 998 case 0x3: 999 op = ASM_OP_TNAT_Z_UNC, 1000 fmt = ASM_FMT_I17; 1001 break; 1002 } 1003 } else { 1004 switch (FIELD(bits, 12, 2)) { /* c + y */ 1005 case 0x0: 1006 op = ASM_OP_TBIT_Z_AND, 1007 fmt = ASM_FMT_I16; 1008 break; 1009 case 0x1: 1010 op = ASM_OP_TBIT_NZ_AND, 1011 fmt = ASM_FMT_I16; 1012 break; 1013 case 0x2: 1014 op = ASM_OP_TNAT_Z_AND, 1015 fmt = ASM_FMT_I17; 1016 break; 1017 case 0x3: 1018 op = ASM_OP_TNAT_NZ_AND, 1019 fmt = ASM_FMT_I17; 1020 break; 1021 } 1022 } 1023 break; 1024 case 0x1: 1025 if (FIELD(bits, 36, 1) == 0) { /* tb */ 1026 switch (FIELD(bits, 12, 2)) { /* c + y */ 1027 case 0x0: 1028 op = ASM_OP_TBIT_Z_OR, 1029 fmt = ASM_FMT_I16; 1030 break; 1031 case 0x1: 1032 op = ASM_OP_TBIT_NZ_OR, 1033 fmt = ASM_FMT_I16; 1034 break; 1035 case 0x2: 1036 op = ASM_OP_TNAT_Z_OR, 1037 fmt = ASM_FMT_I17; 1038 break; 1039 case 0x3: 1040 op = ASM_OP_TNAT_NZ_OR, 1041 fmt = ASM_FMT_I17; 1042 break; 1043 } 1044 } else { 1045 switch (FIELD(bits, 12, 2)) { /* c + y */ 1046 case 0x0: 1047 op = ASM_OP_TBIT_Z_OR_ANDCM, 1048 fmt = ASM_FMT_I16; 1049 break; 1050 case 0x1: 1051 op = ASM_OP_TBIT_NZ_OR_ANDCM, 1052 fmt = ASM_FMT_I16; 1053 break; 1054 case 0x2: 1055 op = ASM_OP_TNAT_Z_OR_ANDCM, 1056 fmt = ASM_FMT_I17; 1057 break; 1058 case 0x3: 1059 op = ASM_OP_TNAT_NZ_OR_ANDCM, 1060 fmt = ASM_FMT_I17; 1061 break; 1062 } 1063 } 1064 break; 1065 case 0x2: 1066 op = ASM_OP_EXTR, fmt = ASM_FMT_I11; 1067 break; 1068 case 0x3: 1069 if (FIELD(bits, 26, 1) == 0) /* y */ 1070 op = ASM_OP_DEP_Z, fmt = ASM_FMT_I12; 1071 else 1072 op = ASM_OP_DEP_Z, fmt = ASM_FMT_I13; 1073 break; 1074 case 0x6: 1075 op = ASM_OP_SHRP, fmt = ASM_FMT_I10; 1076 break; 1077 case 0x7: 1078 op = ASM_OP_DEP_, fmt = ASM_FMT_I14; 1079 break; 1080 } 1081 break; 1082 case 0x7: 1083 switch (FIELD(bits, 32, 5)) { /* ve + zb + x2a + za */ 1084 case 0x2: 1085 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1086 case 0x0: 1087 op = ASM_OP_PSHR2_U, fmt = ASM_FMT_I5; 1088 break; 1089 case 0x1: case 0x5: case 0x9: case 0xD: 1090 op = ASM_OP_PMPYSHR2_U, fmt = ASM_FMT_I1; 1091 break; 1092 case 0x2: 1093 op = ASM_OP_PSHR2_, fmt = ASM_FMT_I5; 1094 break; 1095 case 0x3: case 0x7: case 0xB: case 0xF: 1096 op = ASM_OP_PMPYSHR2_, fmt = ASM_FMT_I1; 1097 break; 1098 case 0x4: 1099 op = ASM_OP_PSHL2, fmt = ASM_FMT_I7; 1100 break; 1101 } 1102 break; 1103 case 0x6: 1104 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1105 case 0x1: 1106 op = ASM_OP_PSHR2_U, fmt = ASM_FMT_I6; 1107 break; 1108 case 0x3: 1109 op = ASM_OP_PSHR2_, fmt = ASM_FMT_I6; 1110 break; 1111 case 0x9: 1112 op = ASM_OP_POPCNT, fmt = ASM_FMT_I9; 1113 break; 1114 } 1115 break; 1116 case 0x8: 1117 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1118 case 0x1: 1119 op = ASM_OP_PMIN1_U, fmt = ASM_FMT_I2; 1120 break; 1121 case 0x4: 1122 op = ASM_OP_UNPACK1_H, fmt = ASM_FMT_I2; 1123 break; 1124 case 0x5: 1125 op = ASM_OP_PMAX1_U, fmt = ASM_FMT_I2; 1126 break; 1127 case 0x6: 1128 op = ASM_OP_UNPACK1_L, fmt = ASM_FMT_I2; 1129 break; 1130 case 0x8: 1131 op = ASM_OP_MIX1_R, fmt = ASM_FMT_I2; 1132 break; 1133 case 0xA: 1134 op = ASM_OP_MIX1_L, fmt = ASM_FMT_I2; 1135 break; 1136 case 0xB: 1137 op = ASM_OP_PSAD1, fmt = ASM_FMT_I2; 1138 break; 1139 } 1140 break; 1141 case 0xA: 1142 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1143 case 0x0: 1144 op = ASM_OP_PACK2_USS, fmt = ASM_FMT_I2; 1145 break; 1146 case 0x2: 1147 op = ASM_OP_PACK2_SSS, fmt = ASM_FMT_I2; 1148 break; 1149 case 0x3: 1150 op = ASM_OP_PMIN2, fmt = ASM_FMT_I2; 1151 break; 1152 case 0x4: 1153 op = ASM_OP_UNPACK2_H, fmt = ASM_FMT_I2; 1154 break; 1155 case 0x6: 1156 op = ASM_OP_UNPACK2_L, fmt = ASM_FMT_I2; 1157 break; 1158 case 0x7: 1159 op = ASM_OP_PMAX2, fmt = ASM_FMT_I2; 1160 break; 1161 case 0x8: 1162 op = ASM_OP_MIX2_R, fmt = ASM_FMT_I2; 1163 break; 1164 case 0xA: 1165 op = ASM_OP_MIX2_L, fmt = ASM_FMT_I2; 1166 break; 1167 case 0xD: 1168 op = ASM_OP_PMPY2_R, fmt = ASM_FMT_I2; 1169 break; 1170 case 0xF: 1171 op = ASM_OP_PMPY2_L, fmt = ASM_FMT_I2; 1172 break; 1173 } 1174 break; 1175 case 0xC: 1176 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1177 case 0xA: 1178 op = ASM_OP_MUX1, fmt = ASM_FMT_I3; 1179 break; 1180 } 1181 break; 1182 case 0xE: 1183 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1184 case 0x5: 1185 op = ASM_OP_PSHL2, fmt = ASM_FMT_I8; 1186 break; 1187 case 0xA: 1188 op = ASM_OP_MUX2, fmt = ASM_FMT_I4; 1189 break; 1190 } 1191 break; 1192 case 0x10: 1193 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1194 case 0x0: 1195 op = ASM_OP_PSHR4_U, fmt = ASM_FMT_I5; 1196 break; 1197 case 0x2: 1198 op = ASM_OP_PSHR4_, fmt = ASM_FMT_I5; 1199 break; 1200 case 0x4: 1201 op = ASM_OP_PSHL4, fmt = ASM_FMT_I7; 1202 break; 1203 } 1204 break; 1205 case 0x12: 1206 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1207 case 0x0: 1208 op = ASM_OP_SHR_U, fmt = ASM_FMT_I5; 1209 break; 1210 case 0x2: 1211 op = ASM_OP_SHR_, fmt = ASM_FMT_I5; 1212 break; 1213 case 0x4: 1214 op = ASM_OP_SHL, fmt = ASM_FMT_I7; 1215 break; 1216 } 1217 break; 1218 case 0x14: 1219 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1220 case 0x1: 1221 op = ASM_OP_PSHR4_U, fmt = ASM_FMT_I6; 1222 break; 1223 case 0x3: 1224 op = ASM_OP_PSHR4_, fmt = ASM_FMT_I6; 1225 break; 1226 } 1227 break; 1228 case 0x18: 1229 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1230 case 0x2: 1231 op = ASM_OP_PACK4_SSS, fmt = ASM_FMT_I2; 1232 break; 1233 case 0x4: 1234 op = ASM_OP_UNPACK4_H, fmt = ASM_FMT_I2; 1235 break; 1236 case 0x6: 1237 op = ASM_OP_UNPACK4_L, fmt = ASM_FMT_I2; 1238 break; 1239 case 0x8: 1240 op = ASM_OP_MIX4_R, fmt = ASM_FMT_I2; 1241 break; 1242 case 0xA: 1243 op = ASM_OP_MIX4_L, fmt = ASM_FMT_I2; 1244 break; 1245 } 1246 break; 1247 case 0x1C: 1248 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1249 case 0x5: 1250 op = ASM_OP_PSHL4, fmt = ASM_FMT_I8; 1251 break; 1252 } 1253 break; 1254 } 1255 break; 1256 } 1257 1258 if (op != ASM_OP_NONE) 1259 return (asm_extract(op, fmt, bits, b, slot)); 1260 return (0); 1261 } 1262 1263 /* 1264 * Decode M-unit instructions. 1265 */ 1266 static int 1267 asm_decodeM(uint64_t ip, struct asm_bundle *b, int slot) 1268 { 1269 uint64_t bits; 1270 enum asm_fmt fmt; 1271 enum asm_op op; 1272 1273 bits = SLOT(ip, slot); 1274 if ((int)OPCODE(bits) >= 8) 1275 return (asm_decodeA(bits, b, slot)); 1276 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 1277 1278 switch((int)OPCODE(bits)) { 1279 case 0x0: 1280 switch (FIELD(bits, 33, 3)) { /* x3 */ 1281 case 0x0: 1282 switch (FIELD(bits, 27, 6)) { /* x6 (x4 + x2) */ 1283 case 0x0: 1284 op = ASM_OP_BREAK_M, fmt = ASM_FMT_M37; 1285 break; 1286 case 0x1: 1287 op = ASM_OP_NOP_M, fmt = ASM_FMT_M37; 1288 break; 1289 case 0x4: case 0x14: case 0x24: case 0x34: 1290 op = ASM_OP_SUM, fmt = ASM_FMT_M44; 1291 break; 1292 case 0x5: case 0x15: case 0x25: case 0x35: 1293 op = ASM_OP_RUM, fmt = ASM_FMT_M44; 1294 break; 1295 case 0x6: case 0x16: case 0x26: case 0x36: 1296 op = ASM_OP_SSM, fmt = ASM_FMT_M44; 1297 break; 1298 case 0x7: case 0x17: case 0x27: case 0x37: 1299 op = ASM_OP_RSM, fmt = ASM_FMT_M44; 1300 break; 1301 case 0xA: 1302 op = ASM_OP_LOADRS, fmt = ASM_FMT_M25; 1303 break; 1304 case 0xC: 1305 op = ASM_OP_FLUSHRS, fmt = ASM_FMT_M25; 1306 break; 1307 case 0x10: 1308 op = ASM_OP_INVALA_, fmt = ASM_FMT_M24; 1309 break; 1310 case 0x12: 1311 op = ASM_OP_INVALA_E, fmt = ASM_FMT_M26; 1312 break; 1313 case 0x13: 1314 op = ASM_OP_INVALA_E, fmt = ASM_FMT_M27; 1315 break; 1316 case 0x20: 1317 op = ASM_OP_FWB, fmt = ASM_FMT_M24; 1318 break; 1319 case 0x22: 1320 op = ASM_OP_MF_, fmt = ASM_FMT_M24; 1321 break; 1322 case 0x23: 1323 op = ASM_OP_MF_A, fmt = ASM_FMT_M24; 1324 break; 1325 case 0x28: 1326 op = ASM_OP_MOV_M, fmt = ASM_FMT_M30; 1327 break; 1328 case 0x30: 1329 op = ASM_OP_SRLZ_D, fmt = ASM_FMT_M24; 1330 break; 1331 case 0x31: 1332 op = ASM_OP_SRLZ_I, fmt = ASM_FMT_M24; 1333 break; 1334 case 0x33: 1335 op = ASM_OP_SYNC_I, fmt = ASM_FMT_M24; 1336 break; 1337 } 1338 break; 1339 case 0x4: 1340 op = ASM_OP_CHK_A_NC, fmt = ASM_FMT_M22; 1341 break; 1342 case 0x5: 1343 op = ASM_OP_CHK_A_CLR, fmt = ASM_FMT_M22; 1344 break; 1345 case 0x6: 1346 op = ASM_OP_CHK_A_NC, fmt = ASM_FMT_M23; 1347 break; 1348 case 0x7: 1349 op = ASM_OP_CHK_A_CLR, fmt = ASM_FMT_M23; 1350 break; 1351 } 1352 break; 1353 case 0x1: 1354 switch (FIELD(bits, 33, 3)) { /* x3 */ 1355 case 0x0: 1356 switch (FIELD(bits, 27, 6)) { /* x6 (x4 + x2) */ 1357 case 0x0: 1358 op = ASM_OP_MOV_RR, fmt = ASM_FMT_M42; 1359 break; 1360 case 0x1: 1361 op = ASM_OP_MOV_DBR, fmt = ASM_FMT_M42; 1362 break; 1363 case 0x2: 1364 op = ASM_OP_MOV_IBR, fmt = ASM_FMT_M42; 1365 break; 1366 case 0x3: 1367 op = ASM_OP_MOV_PKR, fmt = ASM_FMT_M42; 1368 break; 1369 case 0x4: 1370 op = ASM_OP_MOV_PMC, fmt = ASM_FMT_M42; 1371 break; 1372 case 0x5: 1373 op = ASM_OP_MOV_PMD, fmt = ASM_FMT_M42; 1374 break; 1375 case 0x6: 1376 op = ASM_OP_MOV_MSR, fmt = ASM_FMT_M42; 1377 break; 1378 case 0x9: 1379 op = ASM_OP_PTC_L, fmt = ASM_FMT_M45; 1380 break; 1381 case 0xA: 1382 op = ASM_OP_PTC_G, fmt = ASM_FMT_M45; 1383 break; 1384 case 0xB: 1385 op = ASM_OP_PTC_GA, fmt = ASM_FMT_M45; 1386 break; 1387 case 0xC: 1388 op = ASM_OP_PTR_D, fmt = ASM_FMT_M45; 1389 break; 1390 case 0xD: 1391 op = ASM_OP_PTR_I, fmt = ASM_FMT_M45; 1392 break; 1393 case 0xE: 1394 op = ASM_OP_ITR_D, fmt = ASM_FMT_M42; 1395 break; 1396 case 0xF: 1397 op = ASM_OP_ITR_I, fmt = ASM_FMT_M42; 1398 break; 1399 case 0x10: 1400 op = ASM_OP_MOV_RR, fmt = ASM_FMT_M43; 1401 break; 1402 case 0x11: 1403 op = ASM_OP_MOV_DBR, fmt = ASM_FMT_M43; 1404 break; 1405 case 0x12: 1406 op = ASM_OP_MOV_IBR, fmt = ASM_FMT_M43; 1407 break; 1408 case 0x13: 1409 op = ASM_OP_MOV_PKR, fmt = ASM_FMT_M43; 1410 break; 1411 case 0x14: 1412 op = ASM_OP_MOV_PMC, fmt = ASM_FMT_M43; 1413 break; 1414 case 0x15: 1415 op = ASM_OP_MOV_PMD, fmt = ASM_FMT_M43; 1416 break; 1417 case 0x16: 1418 op = ASM_OP_MOV_MSR, fmt = ASM_FMT_M43; 1419 break; 1420 case 0x17: 1421 op = ASM_OP_MOV_CPUID, fmt = ASM_FMT_M43; 1422 break; 1423 case 0x18: 1424 op = ASM_OP_PROBE_R, fmt = ASM_FMT_M39; 1425 break; 1426 case 0x19: 1427 op = ASM_OP_PROBE_W, fmt = ASM_FMT_M39; 1428 break; 1429 case 0x1A: 1430 op = ASM_OP_THASH, fmt = ASM_FMT_M46; 1431 break; 1432 case 0x1B: 1433 op = ASM_OP_TTAG, fmt = ASM_FMT_M46; 1434 break; 1435 case 0x1E: 1436 op = ASM_OP_TPA, fmt = ASM_FMT_M46; 1437 break; 1438 case 0x1F: 1439 op = ASM_OP_TAK, fmt = ASM_FMT_M46; 1440 break; 1441 case 0x21: 1442 op = ASM_OP_MOV_PSR_UM, fmt = ASM_FMT_M36; 1443 break; 1444 case 0x22: 1445 op = ASM_OP_MOV_M, fmt = ASM_FMT_M31; 1446 break; 1447 case 0x24: 1448 op = ASM_OP_MOV_, fmt = ASM_FMT_M33; 1449 break; 1450 case 0x25: 1451 op = ASM_OP_MOV_PSR, fmt = ASM_FMT_M36; 1452 break; 1453 case 0x29: 1454 op = ASM_OP_MOV_PSR_UM, fmt = ASM_FMT_M35; 1455 break; 1456 case 0x2A: 1457 op = ASM_OP_MOV_M, fmt = ASM_FMT_M29; 1458 break; 1459 case 0x2C: 1460 op = ASM_OP_MOV_, fmt = ASM_FMT_M32; 1461 break; 1462 case 0x2D: 1463 op = ASM_OP_MOV_PSR_L, fmt = ASM_FMT_M35; 1464 break; 1465 case 0x2E: 1466 op = ASM_OP_ITC_D, fmt = ASM_FMT_M41; 1467 break; 1468 case 0x2F: 1469 op = ASM_OP_ITC_I, fmt = ASM_FMT_M41; 1470 break; 1471 case 0x30: 1472 if (FIELD(bits, 36, 1) == 0) /* x */ 1473 op = ASM_OP_FC_, fmt = ASM_FMT_M28; 1474 else 1475 op = ASM_OP_FC_I, fmt = ASM_FMT_M28; 1476 break; 1477 case 0x31: 1478 op = ASM_OP_PROBE_RW_FAULT, fmt = ASM_FMT_M40; 1479 break; 1480 case 0x32: 1481 op = ASM_OP_PROBE_R_FAULT, fmt = ASM_FMT_M40; 1482 break; 1483 case 0x33: 1484 op = ASM_OP_PROBE_W_FAULT, fmt = ASM_FMT_M40; 1485 break; 1486 case 0x34: 1487 op = ASM_OP_PTC_E, fmt = ASM_FMT_M28; 1488 break; 1489 case 0x38: 1490 op = ASM_OP_PROBE_R, fmt = ASM_FMT_M38; 1491 break; 1492 case 0x39: 1493 op = ASM_OP_PROBE_W, fmt = ASM_FMT_M38; 1494 break; 1495 } 1496 break; 1497 case 0x1: 1498 op = ASM_OP_CHK_S_M, fmt = ASM_FMT_M20; 1499 break; 1500 case 0x3: 1501 op = ASM_OP_CHK_S, fmt = ASM_FMT_M21; 1502 break; 1503 case 0x6: 1504 op = ASM_OP_ALLOC, fmt = ASM_FMT_M34; 1505 break; 1506 } 1507 break; 1508 case 0x4: 1509 if (FIELD(bits, 27, 1) == 0) { /* x */ 1510 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1511 case 0x0: 1512 op = ASM_OP_LD1_, fmt = ASM_FMT_M1; 1513 break; 1514 case 0x1: 1515 op = ASM_OP_LD2_, fmt = ASM_FMT_M1; 1516 break; 1517 case 0x2: 1518 op = ASM_OP_LD4_, fmt = ASM_FMT_M1; 1519 break; 1520 case 0x3: 1521 op = ASM_OP_LD8_, fmt = ASM_FMT_M1; 1522 break; 1523 case 0x4: 1524 op = ASM_OP_LD1_S, fmt = ASM_FMT_M1; 1525 break; 1526 case 0x5: 1527 op = ASM_OP_LD2_S, fmt = ASM_FMT_M1; 1528 break; 1529 case 0x6: 1530 op = ASM_OP_LD4_S, fmt = ASM_FMT_M1; 1531 break; 1532 case 0x7: 1533 op = ASM_OP_LD8_S, fmt = ASM_FMT_M1; 1534 break; 1535 case 0x8: 1536 op = ASM_OP_LD1_A, fmt = ASM_FMT_M1; 1537 break; 1538 case 0x9: 1539 op = ASM_OP_LD2_A, fmt = ASM_FMT_M1; 1540 break; 1541 case 0xA: 1542 op = ASM_OP_LD4_A, fmt = ASM_FMT_M1; 1543 break; 1544 case 0xB: 1545 op = ASM_OP_LD8_A, fmt = ASM_FMT_M1; 1546 break; 1547 case 0xC: 1548 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M1; 1549 break; 1550 case 0xD: 1551 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M1; 1552 break; 1553 case 0xE: 1554 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M1; 1555 break; 1556 case 0xF: 1557 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M1; 1558 break; 1559 case 0x10: 1560 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M1; 1561 break; 1562 case 0x11: 1563 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M1; 1564 break; 1565 case 0x12: 1566 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M1; 1567 break; 1568 case 0x13: 1569 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M1; 1570 break; 1571 case 0x14: 1572 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M1; 1573 break; 1574 case 0x15: 1575 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M1; 1576 break; 1577 case 0x16: 1578 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M1; 1579 break; 1580 case 0x17: 1581 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M1; 1582 break; 1583 case 0x1B: 1584 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M1; 1585 break; 1586 case 0x20: 1587 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M1; 1588 break; 1589 case 0x21: 1590 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M1; 1591 break; 1592 case 0x22: 1593 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M1; 1594 break; 1595 case 0x23: 1596 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M1; 1597 break; 1598 case 0x24: 1599 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M1; 1600 break; 1601 case 0x25: 1602 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M1; 1603 break; 1604 case 0x26: 1605 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M1; 1606 break; 1607 case 0x27: 1608 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M1; 1609 break; 1610 case 0x28: 1611 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M1; 1612 break; 1613 case 0x29: 1614 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M1; 1615 break; 1616 case 0x2A: 1617 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M1; 1618 break; 1619 case 0x2B: 1620 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M1; 1621 break; 1622 case 0x30: 1623 op = ASM_OP_ST1_, fmt = ASM_FMT_M4; 1624 break; 1625 case 0x31: 1626 op = ASM_OP_ST2_, fmt = ASM_FMT_M4; 1627 break; 1628 case 0x32: 1629 op = ASM_OP_ST4_, fmt = ASM_FMT_M4; 1630 break; 1631 case 0x33: 1632 op = ASM_OP_ST8_, fmt = ASM_FMT_M4; 1633 break; 1634 case 0x34: 1635 op = ASM_OP_ST1_REL, fmt = ASM_FMT_M4; 1636 break; 1637 case 0x35: 1638 op = ASM_OP_ST2_REL, fmt = ASM_FMT_M4; 1639 break; 1640 case 0x36: 1641 op = ASM_OP_ST4_REL, fmt = ASM_FMT_M4; 1642 break; 1643 case 0x37: 1644 op = ASM_OP_ST8_REL, fmt = ASM_FMT_M4; 1645 break; 1646 case 0x3B: 1647 op = ASM_OP_ST8_SPILL, fmt = ASM_FMT_M4; 1648 break; 1649 case 0x40: 1650 op = ASM_OP_LD1_, fmt = ASM_FMT_M2; 1651 break; 1652 case 0x41: 1653 op = ASM_OP_LD2_, fmt = ASM_FMT_M2; 1654 break; 1655 case 0x42: 1656 op = ASM_OP_LD4_, fmt = ASM_FMT_M2; 1657 break; 1658 case 0x43: 1659 op = ASM_OP_LD8_, fmt = ASM_FMT_M2; 1660 break; 1661 case 0x44: 1662 op = ASM_OP_LD1_S, fmt = ASM_FMT_M2; 1663 break; 1664 case 0x45: 1665 op = ASM_OP_LD2_S, fmt = ASM_FMT_M2; 1666 break; 1667 case 0x46: 1668 op = ASM_OP_LD4_S, fmt = ASM_FMT_M2; 1669 break; 1670 case 0x47: 1671 op = ASM_OP_LD8_S, fmt = ASM_FMT_M2; 1672 break; 1673 case 0x48: 1674 op = ASM_OP_LD1_A, fmt = ASM_FMT_M2; 1675 break; 1676 case 0x49: 1677 op = ASM_OP_LD2_A, fmt = ASM_FMT_M2; 1678 break; 1679 case 0x4A: 1680 op = ASM_OP_LD4_A, fmt = ASM_FMT_M2; 1681 break; 1682 case 0x4B: 1683 op = ASM_OP_LD8_A, fmt = ASM_FMT_M2; 1684 break; 1685 case 0x4C: 1686 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M2; 1687 break; 1688 case 0x4D: 1689 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M2; 1690 break; 1691 case 0x4E: 1692 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M2; 1693 break; 1694 case 0x4F: 1695 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M2; 1696 break; 1697 case 0x50: 1698 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M2; 1699 break; 1700 case 0x51: 1701 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M2; 1702 break; 1703 case 0x52: 1704 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M2; 1705 break; 1706 case 0x53: 1707 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M2; 1708 break; 1709 case 0x54: 1710 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M2; 1711 break; 1712 case 0x55: 1713 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M2; 1714 break; 1715 case 0x56: 1716 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M2; 1717 break; 1718 case 0x57: 1719 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M2; 1720 break; 1721 case 0x5B: 1722 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M2; 1723 break; 1724 case 0x60: 1725 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M2; 1726 break; 1727 case 0x61: 1728 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M2; 1729 break; 1730 case 0x62: 1731 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M2; 1732 break; 1733 case 0x63: 1734 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M2; 1735 break; 1736 case 0x64: 1737 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M2; 1738 break; 1739 case 0x65: 1740 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M2; 1741 break; 1742 case 0x66: 1743 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M2; 1744 break; 1745 case 0x67: 1746 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M2; 1747 break; 1748 case 0x68: 1749 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M2; 1750 break; 1751 case 0x69: 1752 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M2; 1753 break; 1754 case 0x6A: 1755 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M2; 1756 break; 1757 case 0x6B: 1758 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M2; 1759 break; 1760 } 1761 } else { 1762 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1763 case 0x0: 1764 op = ASM_OP_CMPXCHG1_ACQ, fmt = ASM_FMT_M16; 1765 break; 1766 case 0x1: 1767 op = ASM_OP_CMPXCHG2_ACQ, fmt = ASM_FMT_M16; 1768 break; 1769 case 0x2: 1770 op = ASM_OP_CMPXCHG4_ACQ, fmt = ASM_FMT_M16; 1771 break; 1772 case 0x3: 1773 op = ASM_OP_CMPXCHG8_ACQ, fmt = ASM_FMT_M16; 1774 break; 1775 case 0x4: 1776 op = ASM_OP_CMPXCHG1_REL, fmt = ASM_FMT_M16; 1777 break; 1778 case 0x5: 1779 op = ASM_OP_CMPXCHG2_REL, fmt = ASM_FMT_M16; 1780 break; 1781 case 0x6: 1782 op = ASM_OP_CMPXCHG4_REL, fmt = ASM_FMT_M16; 1783 break; 1784 case 0x7: 1785 op = ASM_OP_CMPXCHG8_REL, fmt = ASM_FMT_M16; 1786 break; 1787 case 0x8: 1788 op = ASM_OP_XCHG1, fmt = ASM_FMT_M16; 1789 break; 1790 case 0x9: 1791 op = ASM_OP_XCHG2, fmt = ASM_FMT_M16; 1792 break; 1793 case 0xA: 1794 op = ASM_OP_XCHG4, fmt = ASM_FMT_M16; 1795 break; 1796 case 0xB: 1797 op = ASM_OP_XCHG8, fmt = ASM_FMT_M16; 1798 break; 1799 case 0x12: 1800 op = ASM_OP_FETCHADD4_ACQ, fmt = ASM_FMT_M17; 1801 break; 1802 case 0x13: 1803 op = ASM_OP_FETCHADD8_ACQ, fmt = ASM_FMT_M17; 1804 break; 1805 case 0x16: 1806 op = ASM_OP_FETCHADD4_REL, fmt = ASM_FMT_M17; 1807 break; 1808 case 0x17: 1809 op = ASM_OP_FETCHADD8_REL, fmt = ASM_FMT_M17; 1810 break; 1811 case 0x1C: 1812 op = ASM_OP_GETF_SIG, fmt = ASM_FMT_M19; 1813 break; 1814 case 0x1D: 1815 op = ASM_OP_GETF_EXP, fmt = ASM_FMT_M19; 1816 break; 1817 case 0x1E: 1818 op = ASM_OP_GETF_S, fmt = ASM_FMT_M19; 1819 break; 1820 case 0x1F: 1821 op = ASM_OP_GETF_D, fmt = ASM_FMT_M19; 1822 break; 1823 case 0x20: 1824 op = ASM_OP_CMP8XCHG16_ACQ, fmt = ASM_FMT_M16; 1825 break; 1826 case 0x24: 1827 op = ASM_OP_CMP8XCHG16_REL, fmt = ASM_FMT_M16; 1828 break; 1829 case 0x28: 1830 op = ASM_OP_LD16_, fmt = ASM_FMT_M1; 1831 break; 1832 case 0x2C: 1833 op = ASM_OP_LD16_ACQ, fmt = ASM_FMT_M1; 1834 break; 1835 case 0x30: 1836 op = ASM_OP_ST16_, fmt = ASM_FMT_M4; 1837 break; 1838 case 0x34: 1839 op = ASM_OP_ST16_REL, fmt = ASM_FMT_M4; 1840 break; 1841 } 1842 } 1843 break; 1844 case 0x5: 1845 switch (FIELD(bits, 30, 6)) { /* x6 */ 1846 case 0x0: 1847 op = ASM_OP_LD1_, fmt = ASM_FMT_M3; 1848 break; 1849 case 0x1: 1850 op = ASM_OP_LD2_, fmt = ASM_FMT_M3; 1851 break; 1852 case 0x2: 1853 op = ASM_OP_LD4_, fmt = ASM_FMT_M3; 1854 break; 1855 case 0x3: 1856 op = ASM_OP_LD8_, fmt = ASM_FMT_M3; 1857 break; 1858 case 0x4: 1859 op = ASM_OP_LD1_S, fmt = ASM_FMT_M3; 1860 break; 1861 case 0x5: 1862 op = ASM_OP_LD2_S, fmt = ASM_FMT_M3; 1863 break; 1864 case 0x6: 1865 op = ASM_OP_LD4_S, fmt = ASM_FMT_M3; 1866 break; 1867 case 0x7: 1868 op = ASM_OP_LD8_S, fmt = ASM_FMT_M3; 1869 break; 1870 case 0x8: 1871 op = ASM_OP_LD1_A, fmt = ASM_FMT_M3; 1872 break; 1873 case 0x9: 1874 op = ASM_OP_LD2_A, fmt = ASM_FMT_M3; 1875 break; 1876 case 0xA: 1877 op = ASM_OP_LD4_A, fmt = ASM_FMT_M3; 1878 break; 1879 case 0xB: 1880 op = ASM_OP_LD8_A, fmt = ASM_FMT_M3; 1881 break; 1882 case 0xC: 1883 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M3; 1884 break; 1885 case 0xD: 1886 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M3; 1887 break; 1888 case 0xE: 1889 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M3; 1890 break; 1891 case 0xF: 1892 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M3; 1893 break; 1894 case 0x10: 1895 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M3; 1896 break; 1897 case 0x11: 1898 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M3; 1899 break; 1900 case 0x12: 1901 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M3; 1902 break; 1903 case 0x13: 1904 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M3; 1905 break; 1906 case 0x14: 1907 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M3; 1908 break; 1909 case 0x15: 1910 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M3; 1911 break; 1912 case 0x16: 1913 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M3; 1914 break; 1915 case 0x17: 1916 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M3; 1917 break; 1918 case 0x1B: 1919 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M3; 1920 break; 1921 case 0x20: 1922 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M3; 1923 break; 1924 case 0x21: 1925 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M3; 1926 break; 1927 case 0x22: 1928 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M3; 1929 break; 1930 case 0x23: 1931 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M3; 1932 break; 1933 case 0x24: 1934 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M3; 1935 break; 1936 case 0x25: 1937 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M3; 1938 break; 1939 case 0x26: 1940 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M3; 1941 break; 1942 case 0x27: 1943 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M3; 1944 break; 1945 case 0x28: 1946 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M3; 1947 break; 1948 case 0x29: 1949 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M3; 1950 break; 1951 case 0x2A: 1952 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M3; 1953 break; 1954 case 0x2B: 1955 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M3; 1956 break; 1957 case 0x30: 1958 op = ASM_OP_ST1_, fmt = ASM_FMT_M5; 1959 break; 1960 case 0x31: 1961 op = ASM_OP_ST2_, fmt = ASM_FMT_M5; 1962 break; 1963 case 0x32: 1964 op = ASM_OP_ST4_, fmt = ASM_FMT_M5; 1965 break; 1966 case 0x33: 1967 op = ASM_OP_ST8_, fmt = ASM_FMT_M5; 1968 break; 1969 case 0x34: 1970 op = ASM_OP_ST1_REL, fmt = ASM_FMT_M5; 1971 break; 1972 case 0x35: 1973 op = ASM_OP_ST2_REL, fmt = ASM_FMT_M5; 1974 break; 1975 case 0x36: 1976 op = ASM_OP_ST4_REL, fmt = ASM_FMT_M5; 1977 break; 1978 case 0x37: 1979 op = ASM_OP_ST8_REL, fmt = ASM_FMT_M5; 1980 break; 1981 case 0x3B: 1982 op = ASM_OP_ST8_SPILL, fmt = ASM_FMT_M5; 1983 break; 1984 } 1985 break; 1986 case 0x6: 1987 if (FIELD(bits, 27, 1) == 0) { /* x */ 1988 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1989 case 0x0: 1990 op = ASM_OP_LDFE_, fmt = ASM_FMT_M6; 1991 break; 1992 case 0x1: 1993 op = ASM_OP_LDF8_, fmt = ASM_FMT_M6; 1994 break; 1995 case 0x2: 1996 op = ASM_OP_LDFS_, fmt = ASM_FMT_M6; 1997 break; 1998 case 0x3: 1999 op = ASM_OP_LDFD_, fmt = ASM_FMT_M6; 2000 break; 2001 case 0x4: 2002 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M6; 2003 break; 2004 case 0x5: 2005 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M6; 2006 break; 2007 case 0x6: 2008 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M6; 2009 break; 2010 case 0x7: 2011 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M6; 2012 break; 2013 case 0x8: 2014 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M6; 2015 break; 2016 case 0x9: 2017 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M6; 2018 break; 2019 case 0xA: 2020 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M6; 2021 break; 2022 case 0xB: 2023 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M6; 2024 break; 2025 case 0xC: 2026 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M6; 2027 break; 2028 case 0xD: 2029 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M6; 2030 break; 2031 case 0xE: 2032 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M6; 2033 break; 2034 case 0xF: 2035 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M6; 2036 break; 2037 case 0x1B: 2038 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M6; 2039 break; 2040 case 0x20: 2041 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M6; 2042 break; 2043 case 0x21: 2044 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M6; 2045 break; 2046 case 0x22: 2047 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M6; 2048 break; 2049 case 0x23: 2050 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M6; 2051 break; 2052 case 0x24: 2053 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M6; 2054 break; 2055 case 0x25: 2056 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M6; 2057 break; 2058 case 0x26: 2059 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M6; 2060 break; 2061 case 0x27: 2062 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M6; 2063 break; 2064 case 0x2C: 2065 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M13; 2066 break; 2067 case 0x2D: 2068 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M13; 2069 break; 2070 case 0x2E: 2071 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M13; 2072 break; 2073 case 0x2F: 2074 op = ASM_OP_LFETCH_FAULT_EXCL, 2075 fmt = ASM_FMT_M13; 2076 break; 2077 case 0x30: 2078 op = ASM_OP_STFE, fmt = ASM_FMT_M9; 2079 break; 2080 case 0x31: 2081 op = ASM_OP_STF8, fmt = ASM_FMT_M9; 2082 break; 2083 case 0x32: 2084 op = ASM_OP_STFS, fmt = ASM_FMT_M9; 2085 break; 2086 case 0x33: 2087 op = ASM_OP_STFD, fmt = ASM_FMT_M9; 2088 break; 2089 case 0x3B: 2090 op = ASM_OP_STF_SPILL, fmt = ASM_FMT_M9; 2091 break; 2092 case 0x40: 2093 op = ASM_OP_LDFE_, fmt = ASM_FMT_M7; 2094 break; 2095 case 0x41: 2096 op = ASM_OP_LDF8_, fmt = ASM_FMT_M7; 2097 break; 2098 case 0x42: 2099 op = ASM_OP_LDFS_, fmt = ASM_FMT_M7; 2100 break; 2101 case 0x43: 2102 op = ASM_OP_LDFD_, fmt = ASM_FMT_M7; 2103 break; 2104 case 0x44: 2105 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M7; 2106 break; 2107 case 0x45: 2108 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M7; 2109 break; 2110 case 0x46: 2111 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M7; 2112 break; 2113 case 0x47: 2114 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M7; 2115 break; 2116 case 0x48: 2117 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M7; 2118 break; 2119 case 0x49: 2120 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M7; 2121 break; 2122 case 0x4A: 2123 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M7; 2124 break; 2125 case 0x4B: 2126 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M7; 2127 break; 2128 case 0x4C: 2129 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M7; 2130 break; 2131 case 0x4D: 2132 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M7; 2133 break; 2134 case 0x4E: 2135 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M7; 2136 break; 2137 case 0x4F: 2138 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M7; 2139 break; 2140 case 0x5B: 2141 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M7; 2142 break; 2143 case 0x60: 2144 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M7; 2145 break; 2146 case 0x61: 2147 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M7; 2148 break; 2149 case 0x62: 2150 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M7; 2151 break; 2152 case 0x63: 2153 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M7; 2154 break; 2155 case 0x64: 2156 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M7; 2157 break; 2158 case 0x65: 2159 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M7; 2160 break; 2161 case 0x66: 2162 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M7; 2163 break; 2164 case 0x67: 2165 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M7; 2166 break; 2167 case 0x6C: 2168 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M14; 2169 break; 2170 case 0x6D: 2171 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M14; 2172 break; 2173 case 0x6E: 2174 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M14; 2175 break; 2176 case 0x6F: 2177 op = ASM_OP_LFETCH_FAULT_EXCL, 2178 fmt = ASM_FMT_M14; 2179 break; 2180 } 2181 } else { 2182 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 2183 case 0x1: 2184 op = ASM_OP_LDFP8_, fmt = ASM_FMT_M11; 2185 break; 2186 case 0x2: 2187 op = ASM_OP_LDFPS_, fmt = ASM_FMT_M11; 2188 break; 2189 case 0x3: 2190 op = ASM_OP_LDFPD_, fmt = ASM_FMT_M11; 2191 break; 2192 case 0x5: 2193 op = ASM_OP_LDFP8_S, fmt = ASM_FMT_M11; 2194 break; 2195 case 0x6: 2196 op = ASM_OP_LDFPS_S, fmt = ASM_FMT_M11; 2197 break; 2198 case 0x7: 2199 op = ASM_OP_LDFPD_S, fmt = ASM_FMT_M11; 2200 break; 2201 case 0x9: 2202 op = ASM_OP_LDFP8_A, fmt = ASM_FMT_M11; 2203 break; 2204 case 0xA: 2205 op = ASM_OP_LDFPS_A, fmt = ASM_FMT_M11; 2206 break; 2207 case 0xB: 2208 op = ASM_OP_LDFPD_A, fmt = ASM_FMT_M11; 2209 break; 2210 case 0xD: 2211 op = ASM_OP_LDFP8_SA, fmt = ASM_FMT_M11; 2212 break; 2213 case 0xE: 2214 op = ASM_OP_LDFPS_SA, fmt = ASM_FMT_M11; 2215 break; 2216 case 0xF: 2217 op = ASM_OP_LDFPD_SA, fmt = ASM_FMT_M11; 2218 break; 2219 case 0x1C: 2220 op = ASM_OP_SETF_SIG, fmt = ASM_FMT_M18; 2221 break; 2222 case 0x1D: 2223 op = ASM_OP_SETF_EXP, fmt = ASM_FMT_M18; 2224 break; 2225 case 0x1E: 2226 op = ASM_OP_SETF_S, fmt = ASM_FMT_M18; 2227 break; 2228 case 0x1F: 2229 op = ASM_OP_SETF_D, fmt = ASM_FMT_M18; 2230 break; 2231 case 0x21: 2232 op = ASM_OP_LDFP8_C_CLR, fmt = ASM_FMT_M11; 2233 break; 2234 case 0x22: 2235 op = ASM_OP_LDFPS_C_CLR, fmt = ASM_FMT_M11; 2236 break; 2237 case 0x23: 2238 op = ASM_OP_LDFPD_C_CLR, fmt = ASM_FMT_M11; 2239 break; 2240 case 0x25: 2241 op = ASM_OP_LDFP8_C_NC, fmt = ASM_FMT_M11; 2242 break; 2243 case 0x26: 2244 op = ASM_OP_LDFPS_C_NC, fmt = ASM_FMT_M11; 2245 break; 2246 case 0x27: 2247 op = ASM_OP_LDFPD_C_NC, fmt = ASM_FMT_M11; 2248 break; 2249 case 0x41: 2250 op = ASM_OP_LDFP8_, fmt = ASM_FMT_M12; 2251 break; 2252 case 0x42: 2253 op = ASM_OP_LDFPS_, fmt = ASM_FMT_M12; 2254 break; 2255 case 0x43: 2256 op = ASM_OP_LDFPD_, fmt = ASM_FMT_M12; 2257 break; 2258 case 0x45: 2259 op = ASM_OP_LDFP8_S, fmt = ASM_FMT_M12; 2260 break; 2261 case 0x46: 2262 op = ASM_OP_LDFPS_S, fmt = ASM_FMT_M12; 2263 break; 2264 case 0x47: 2265 op = ASM_OP_LDFPD_S, fmt = ASM_FMT_M12; 2266 break; 2267 case 0x49: 2268 op = ASM_OP_LDFP8_A, fmt = ASM_FMT_M12; 2269 break; 2270 case 0x4A: 2271 op = ASM_OP_LDFPS_A, fmt = ASM_FMT_M12; 2272 break; 2273 case 0x4B: 2274 op = ASM_OP_LDFPD_A, fmt = ASM_FMT_M12; 2275 break; 2276 case 0x4D: 2277 op = ASM_OP_LDFP8_SA, fmt = ASM_FMT_M12; 2278 break; 2279 case 0x4E: 2280 op = ASM_OP_LDFPS_SA, fmt = ASM_FMT_M12; 2281 break; 2282 case 0x4F: 2283 op = ASM_OP_LDFPD_SA, fmt = ASM_FMT_M12; 2284 break; 2285 case 0x61: 2286 op = ASM_OP_LDFP8_C_CLR, fmt = ASM_FMT_M12; 2287 break; 2288 case 0x62: 2289 op = ASM_OP_LDFPS_C_CLR, fmt = ASM_FMT_M12; 2290 break; 2291 case 0x63: 2292 op = ASM_OP_LDFPD_C_CLR, fmt = ASM_FMT_M12; 2293 break; 2294 case 0x65: 2295 op = ASM_OP_LDFP8_C_NC, fmt = ASM_FMT_M12; 2296 break; 2297 case 0x66: 2298 op = ASM_OP_LDFPS_C_NC, fmt = ASM_FMT_M12; 2299 break; 2300 case 0x67: 2301 op = ASM_OP_LDFPD_C_NC, fmt = ASM_FMT_M12; 2302 break; 2303 } 2304 } 2305 break; 2306 case 0x7: 2307 switch (FIELD(bits, 30, 6)) { /* x6 */ 2308 case 0x0: 2309 op = ASM_OP_LDFE_, fmt = ASM_FMT_M8; 2310 break; 2311 case 0x1: 2312 op = ASM_OP_LDF8_, fmt = ASM_FMT_M8; 2313 break; 2314 case 0x2: 2315 op = ASM_OP_LDFS_, fmt = ASM_FMT_M8; 2316 break; 2317 case 0x3: 2318 op = ASM_OP_LDFD_, fmt = ASM_FMT_M8; 2319 break; 2320 case 0x4: 2321 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M8; 2322 break; 2323 case 0x5: 2324 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M8; 2325 break; 2326 case 0x6: 2327 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M8; 2328 break; 2329 case 0x7: 2330 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M8; 2331 break; 2332 case 0x8: 2333 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M8; 2334 break; 2335 case 0x9: 2336 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M8; 2337 break; 2338 case 0xA: 2339 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M8; 2340 break; 2341 case 0xB: 2342 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M8; 2343 break; 2344 case 0xC: 2345 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M8; 2346 break; 2347 case 0xD: 2348 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M8; 2349 break; 2350 case 0xE: 2351 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M8; 2352 break; 2353 case 0xF: 2354 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M8; 2355 break; 2356 case 0x1B: 2357 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M8; 2358 break; 2359 case 0x20: 2360 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M8; 2361 break; 2362 case 0x21: 2363 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M8; 2364 break; 2365 case 0x22: 2366 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M8; 2367 break; 2368 case 0x23: 2369 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M8; 2370 break; 2371 case 0x24: 2372 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M8; 2373 break; 2374 case 0x25: 2375 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M8; 2376 break; 2377 case 0x26: 2378 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M8; 2379 break; 2380 case 0x27: 2381 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M8; 2382 break; 2383 case 0x2C: 2384 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M15; 2385 break; 2386 case 0x2D: 2387 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M15; 2388 break; 2389 case 0x2E: 2390 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M15; 2391 break; 2392 case 0x2F: 2393 op = ASM_OP_LFETCH_FAULT_EXCL, fmt = ASM_FMT_M15; 2394 break; 2395 case 0x30: 2396 op = ASM_OP_STFE, fmt = ASM_FMT_M10; 2397 break; 2398 case 0x31: 2399 op = ASM_OP_STF8, fmt = ASM_FMT_M10; 2400 break; 2401 case 0x32: 2402 op = ASM_OP_STFS, fmt = ASM_FMT_M10; 2403 break; 2404 case 0x33: 2405 op = ASM_OP_STFD, fmt = ASM_FMT_M10; 2406 break; 2407 case 0x3B: 2408 op = ASM_OP_STF_SPILL, fmt = ASM_FMT_M10; 2409 break; 2410 } 2411 break; 2412 } 2413 2414 if (op != ASM_OP_NONE) 2415 return (asm_extract(op, fmt, bits, b, slot)); 2416 return (0); 2417 } 2418 2419 /* 2420 * Decode X-unit instructions. 2421 */ 2422 static int 2423 asm_decodeX(uint64_t ip, struct asm_bundle *b, int slot) 2424 { 2425 uint64_t bits; 2426 enum asm_fmt fmt; 2427 enum asm_op op; 2428 2429 KASSERT(slot == 2); 2430 bits = SLOT(ip, slot); 2431 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 2432 /* Initialize slot 1 (slot - 1) */ 2433 b->b_inst[slot - 1].i_format = ASM_FMT_NONE; 2434 b->b_inst[slot - 1].i_bits = SLOT(ip, slot - 1); 2435 2436 switch((int)OPCODE(bits)) { 2437 case 0x0: 2438 if (FIELD(bits, 33, 3) == 0) { /* x3 */ 2439 switch (FIELD(bits, 27, 6)) { /* x6 */ 2440 case 0x0: 2441 op = ASM_OP_BREAK_X, fmt = ASM_FMT_X1; 2442 break; 2443 case 0x1: 2444 op = ASM_OP_NOP_X, fmt = ASM_FMT_X1; 2445 break; 2446 } 2447 } 2448 break; 2449 case 0x6: 2450 if (FIELD(bits, 20, 1) == 0) 2451 op = ASM_OP_MOVL, fmt = ASM_FMT_X2; 2452 break; 2453 case 0xC: 2454 if (FIELD(bits, 6, 3) == 0) /* btype */ 2455 op = ASM_OP_BRL_COND, fmt = ASM_FMT_X3; 2456 break; 2457 case 0xD: 2458 op = ASM_OP_BRL_CALL, fmt = ASM_FMT_X4; 2459 break; 2460 } 2461 2462 if (op != ASM_OP_NONE) 2463 return (asm_extract(op, fmt, bits, b, slot)); 2464 return (0); 2465 } 2466 2467 int 2468 asm_decode(uint64_t ip, struct asm_bundle *b) 2469 { 2470 const char *tp; 2471 unsigned int slot; 2472 int ok; 2473 2474 memset(b, 0, sizeof(*b)); 2475 2476 b->b_templ = asm_templname[TMPL(ip)]; 2477 if (b->b_templ == 0) 2478 return (0); 2479 2480 slot = 0; 2481 tp = b->b_templ; 2482 2483 ok = 1; 2484 while (ok && *tp != 0) { 2485 switch (*tp++) { 2486 case 'B': 2487 ok = asm_decodeB(ip, b, slot++); 2488 break; 2489 case 'F': 2490 ok = asm_decodeF(ip, b, slot++); 2491 break; 2492 case 'I': 2493 ok = asm_decodeI(ip, b, slot++); 2494 break; 2495 case 'L': 2496 ok = (slot++ == 1) ? 1 : 0; 2497 break; 2498 case 'M': 2499 ok = asm_decodeM(ip, b, slot++); 2500 break; 2501 case 'X': 2502 ok = asm_decodeX(ip, b, slot++); 2503 break; 2504 case ';': 2505 ok = 1; 2506 break; 2507 default: 2508 ok = 0; 2509 break; 2510 } 2511 } 2512 return (ok); 2513 } 2514