1 /* $NetBSD: piixpcib.c,v 1.9 2006/10/12 01:30:44 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto, Matthew R. Green, and Jared D. McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support 41 * 42 * Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.9 2006/10/12 01:30:44 christos Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/sysctl.h> 53 #include <machine/bus.h> 54 55 #include <machine/frame.h> 56 #include <machine/bioscall.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <i386/pci/piixreg.h> 63 64 #define PIIX4_PIRQRC 0x60 65 66 struct piixpcib_softc { 67 struct device sc_dev; 68 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_pcitag; 71 72 int sc_smi_cmd; 73 int sc_smi_data; 74 int sc_command; 75 int sc_flags; 76 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 80 void *sc_powerhook; 81 struct pci_conf_state sc_pciconf; 82 83 pcireg_t sc_pirqrc; 84 uint8_t sc_elcr[2]; 85 }; 86 87 static int piixpcibmatch(struct device *, struct cfdata *, void *); 88 static void piixpcibattach(struct device *, struct device *, void *); 89 90 static void piixpcib_powerhook(int, void *); 91 92 static void speedstep_configure(struct piixpcib_softc *, 93 struct pci_attach_args *); 94 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 95 96 struct piixpcib_softc *speedstep_cookie; /* XXX */ 97 98 /* Defined in arch/i386/pci/pcib.c. */ 99 extern void pcibattach(struct device *, struct device *, void *); 100 101 CFATTACH_DECL(piixpcib, sizeof(struct piixpcib_softc), 102 piixpcibmatch, piixpcibattach, NULL, NULL); 103 104 /* 105 * Autoconf callbacks. 106 */ 107 static int 108 piixpcibmatch(struct device *parent __unused, struct cfdata *match __unused, 109 void *aux) 110 { 111 struct pci_attach_args *pa; 112 113 pa = (struct pci_attach_args *)aux; 114 115 /* We are ISA bridge, of course */ 116 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 117 (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA && 118 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) { 119 return 0; 120 } 121 122 /* Matches only Intel PIIX4 */ 123 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */ 126 case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */ 127 return 10; 128 } 129 } 130 131 return 0; 132 } 133 134 static void 135 piixpcibattach(struct device *parent, struct device *self, void *aux) 136 { 137 struct pci_attach_args *pa; 138 struct piixpcib_softc *sc; 139 140 pa = (struct pci_attach_args *)aux; 141 sc = (struct piixpcib_softc *)self; 142 143 sc->sc_pc = pa->pa_pc; 144 sc->sc_pcitag = pa->pa_tag; 145 sc->sc_iot = pa->pa_iot; 146 147 pcibattach(parent, self, aux); 148 149 /* Set up SpeedStep. */ 150 speedstep_configure(sc, pa); 151 152 /* Map edge/level control registers */ 153 if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 154 &sc->sc_ioh)) { 155 aprint_error("%s: can't map edge/level control registers\n", 156 sc->sc_dev.dv_xname); 157 return; 158 } 159 160 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 161 piixpcib_powerhook, sc); 162 if (sc->sc_powerhook == NULL) 163 aprint_error("%s: can't establish powerhook\n", 164 sc->sc_dev.dv_xname); 165 166 return; 167 } 168 169 static void 170 piixpcib_powerhook(int why, void *opaque) 171 { 172 struct piixpcib_softc *sc; 173 pci_chipset_tag_t pc; 174 pcitag_t tag; 175 176 sc = (struct piixpcib_softc *)opaque; 177 pc = sc->sc_pc; 178 tag = sc->sc_pcitag; 179 180 switch (why) { 181 case PWR_SUSPEND: 182 pci_conf_capture(pc, tag, &sc->sc_pciconf); 183 184 /* capture PIRQX route control registers */ 185 sc->sc_pirqrc = pci_conf_read(pc, tag, PIIX4_PIRQRC); 186 187 /* capture edge/level control registers */ 188 sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 189 sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1); 190 break; 191 case PWR_RESUME: 192 pci_conf_restore(pc, tag, &sc->sc_pciconf); 193 194 /* restore PIRQX route control registers */ 195 pci_conf_write(pc, tag, PIIX4_PIRQRC, sc->sc_pirqrc); 196 197 /* restore edge/level control registers */ 198 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]); 199 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]); 200 break; 201 } 202 203 return; 204 } 205 206 /* 207 * Intel PIIX4 (SMI) SpeedStep support. 208 */ 209 210 #define PIIXPCIB_GSIC 0x47534943 211 #define PIIXPCIB_GETOWNER 0 212 #define PIIXPCIB_GETSTATE 1 213 #define PIIXPCIB_SETSTATE 2 214 #define PIIXPCIB_GETFREQS 4 215 216 #define PIIXPCIB_SPEEDSTEP_HIGH 0 217 #define PIIXPCIB_SPEEDSTEP_LOW 1 218 219 static void 220 piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, int *flags) 221 { 222 struct bioscallregs regs; 223 224 memset(®s, 0, sizeof(struct bioscallregs)); 225 regs.EAX = 0x0000e980; /* IST support */ 226 regs.EDX = PIIXPCIB_GSIC; 227 bioscall(0x15, ®s); 228 229 if (regs.EAX == PIIXPCIB_GSIC) { 230 *sig = regs.EAX; 231 *smicmd = regs.EBX & 0xff; 232 *cmd = (regs.EBX >> 16) & 0xff; 233 *smidata = regs.ECX; 234 *flags = regs.EDX; 235 } else 236 *sig = *smicmd = *cmd = *smidata = *flags = -1; 237 238 return; 239 } 240 241 static int 242 piixpcib_set_ownership(struct piixpcib_softc *sc) 243 { 244 int rv; 245 paddr_t pmagic; 246 static char magic[] = "Copyright (c) 1999 Intel Corporation"; 247 248 pmagic = vtophys((vaddr_t)magic); 249 250 __asm__ __volatile__( 251 "movl $0, %%edi\n\t" 252 "out %%al, (%%dx)\n" 253 : "=D" (rv) 254 : "a" (sc->sc_command), 255 "b" (0), 256 "c" (0), 257 "d" (sc->sc_smi_cmd), 258 "S" (pmagic) 259 ); 260 261 return (rv ? ENXIO : 0); 262 } 263 264 static int 265 piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function) 266 { 267 int new; 268 int rv; 269 int eax; 270 271 #ifdef DIAGNOSTIC 272 if (function != PIIXPCIB_GETSTATE && 273 function != PIIXPCIB_SETSTATE) { 274 aprint_error("%s: GSI called with invalid function %d\n", 275 sc->sc_dev.dv_xname, function); 276 return EINVAL; 277 } 278 #endif 279 280 __asm__ __volatile__( 281 "movl $0, %%edi\n\t" 282 "out %%al, (%%dx)\n" 283 : "=a" (eax), 284 "=b" (new), 285 "=D" (rv) 286 : "a" (sc->sc_command), 287 "b" (function), 288 "c" (*state), 289 "d" (sc->sc_smi_cmd), 290 "S" (0) 291 ); 292 293 *state = new & 1; 294 295 switch (function) { 296 case PIIXPCIB_GETSTATE: 297 if (eax) 298 return ENXIO; 299 break; 300 case PIIXPCIB_SETSTATE: 301 if (rv) 302 return ENXIO; 303 break; 304 } 305 306 return 0; 307 } 308 309 static int 310 piixpcib_get(struct piixpcib_softc *sc) 311 { 312 int rv; 313 int state; 314 315 state = 0; /* XXX gcc */ 316 317 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE); 318 if (rv) 319 return rv; 320 321 return state & 1; 322 } 323 324 static int 325 piixpcib_set(struct piixpcib_softc *sc, int state) 326 { 327 int rv, s; 328 int try; 329 330 if (state != PIIXPCIB_SPEEDSTEP_HIGH && 331 state != PIIXPCIB_SPEEDSTEP_LOW) 332 return ENXIO; 333 if (piixpcib_get(sc) == state) 334 return 0; 335 336 try = 5; 337 338 s = splhigh(); 339 340 do { 341 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE); 342 if (rv) 343 delay(200); 344 } while (rv && --try); 345 346 splx(s); 347 348 return rv; 349 } 350 351 static void 352 speedstep_configure(struct piixpcib_softc *sc, 353 struct pci_attach_args *pa __unused) 354 { 355 const struct sysctlnode *node, *ssnode; 356 int sig, smicmd, cmd, smidata, flags; 357 int rv; 358 359 piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags); 360 361 if (sig != -1) { 362 sc->sc_smi_cmd = smicmd; 363 sc->sc_smi_data = smidata; 364 if (cmd == 0x80) { 365 aprint_debug("%s: GSIC returned cmd 0x80, should be 0x82\n", 366 sc->sc_dev.dv_xname); 367 cmd = 0x82; 368 } 369 sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff); 370 sc->sc_flags = flags; 371 } else { 372 /* setup some defaults */ 373 sc->sc_smi_cmd = 0xb2; 374 sc->sc_smi_data = 0xb3; 375 sc->sc_command = 0x47534982; 376 sc->sc_flags = 0; 377 } 378 379 if (piixpcib_set_ownership(sc) != 0) { 380 aprint_error("%s: unable to claim ownership from the BIOS\n", 381 sc->sc_dev.dv_xname); 382 return; /* If we can't claim ownership from the BIOS, bail */ 383 } 384 385 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 386 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 387 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 388 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 389 goto err; 390 391 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 392 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 393 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 394 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 395 CTL_EOL)) != 0) 396 goto err; 397 398 /* XXX save the sc for IO tag/handle */ 399 speedstep_cookie = sc; 400 401 aprint_verbose("%s: SpeedStep SMI enabled\n", sc->sc_dev.dv_xname); 402 403 return; 404 405 err: 406 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 407 408 return; 409 } 410 411 /* 412 * get/set the SpeedStep state: 0 == low power, 1 == high power. 413 */ 414 static int 415 speedstep_sysctl_helper(SYSCTLFN_ARGS) 416 { 417 struct sysctlnode node; 418 struct piixpcib_softc *sc; 419 uint8_t state, state2; 420 int ostate, nstate, error; 421 422 sc = speedstep_cookie; 423 error = 0; 424 425 state = piixpcib_get(sc); 426 if (state == PIIXPCIB_SPEEDSTEP_HIGH) 427 ostate = 1; 428 else 429 ostate = 0; 430 nstate = ostate; 431 432 node = *rnode; 433 node.sysctl_data = &nstate; 434 435 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 436 if (error || newp == NULL) 437 goto out; 438 439 /* Only two states are available */ 440 if (nstate != 0 && nstate != 1) { 441 error = EINVAL; 442 goto out; 443 } 444 445 state2 = piixpcib_get(sc); 446 if (state2 == PIIXPCIB_SPEEDSTEP_HIGH) 447 ostate = 1; 448 else 449 ostate = 0; 450 451 if (ostate != nstate) 452 { 453 if (nstate == 0) 454 state2 = PIIXPCIB_SPEEDSTEP_LOW; 455 else 456 state2 = PIIXPCIB_SPEEDSTEP_HIGH; 457 458 error = piixpcib_set(sc, state2); 459 } 460 out: 461 return (error); 462 } 463