xref: /netbsd-src/sys/arch/i386/pci/piix.c (revision 3b01aba77a7a698587faaae455bbfe740923c1f5)
1 /*	$NetBSD: piix.c,v 1.2 2000/07/18 11:10:22 soda Exp $	*/
2 
3 /*-
4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by the NetBSD
22  *	Foundation, Inc. and its contributors.
23  * 4. Neither the name of The NetBSD Foundation nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 /*
41  * Copyright (c) 1999, by UCHIYAMA Yasushi
42  * All rights reserved.
43  *
44  * Redistribution and use in source and binary forms, with or without
45  * modification, are permitted provided that the following conditions
46  * are met:
47  * 1. Redistributions of source code must retain the above copyright
48  *    notice, this list of conditions and the following disclaimer.
49  * 2. The name of the developer may NOT be used to endorse or promote products
50  *    derived from this software without specific prior written permission.
51  *
52  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
53  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
56  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62  * SUCH DAMAGE.
63  */
64 
65 /*
66  * Support for the Intel PIIX PCI-ISA bridge interrupt controller.
67  */
68 
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/device.h>
72 #include <sys/malloc.h>
73 
74 #include <machine/intr.h>
75 #include <machine/bus.h>
76 
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pcireg.h>
79 #include <dev/pci/pcidevs.h>
80 
81 #include <i386/pci/pci_intr_fixup.h>
82 #include <i386/pci/piixreg.h>
83 #include <i386/pci/piixvar.h>
84 
85 #ifdef PIIX_DEBUG
86 #define	DPRINTF(arg) printf arg
87 #else
88 #define	DPRINTF(arg)
89 #endif
90 
91 int	piix_getclink __P((pciintr_icu_handle_t, int, int *));
92 int	piix_get_intr __P((pciintr_icu_handle_t, int, int *));
93 int	piix_set_intr __P((pciintr_icu_handle_t, int, int));
94 #ifdef PIIX_DEBUG
95 void	piix_pir_dump __P((struct piix_handle *));
96 #endif
97 
98 const struct pciintr_icu piix_pci_icu = {
99 	piix_getclink,
100 	piix_get_intr,
101 	piix_set_intr,
102 	piix_get_trigger,
103 	piix_set_trigger,
104 };
105 
106 int
107 piix_init(pc, iot, tag, ptagp, phandp)
108 	pci_chipset_tag_t pc;
109 	bus_space_tag_t iot;
110 	pcitag_t tag;
111 	pciintr_icu_tag_t *ptagp;
112 	pciintr_icu_handle_t *phandp;
113 {
114 	struct piix_handle *ph;
115 
116 	ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
117 	if (ph == NULL)
118 		return (1);
119 
120 	ph->ph_iot = iot;
121 	ph->ph_pc = pc;
122 	ph->ph_tag = tag;
123 
124 	if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0,
125 	    &ph->ph_elcr_ioh) != 0) {
126 		free(ph, M_DEVBUF);
127 		return (1);
128 	}
129 
130 #ifdef PIIX_DEBUG
131 	piix_pir_dump(ph);
132 #endif
133 	*ptagp = &piix_pci_icu;
134 	*phandp = ph;
135 	return (0);
136 }
137 
138 int
139 piix_getclink(v, link, clinkp)
140 	pciintr_icu_handle_t v;
141 	int link, *clinkp;
142 {
143 	DPRINTF(("PIIX link value 0x%x: ", link));
144 
145 	/* Pattern 1: simple. */
146 	if (PIIX_LEGAL_LINK(link - 1)) {
147 		*clinkp = link - 1;
148 		DPRINTF(("PIRQ %d (simple)\n", *clinkp));
149 		return (0);
150 	}
151 
152 	/* Pattern 2: configuration register offset */
153 	if (link >= 0x60 && link <= 0x63) {
154 		*clinkp = link - 0x60;
155 		DPRINTF(("PIRQ %d (register offset)\n", *clinkp));
156 		return (0);
157 	}
158 
159 	DPRINTF(("bogus IRQ selection source\n"));
160 	return (1);
161 }
162 
163 int
164 piix_get_intr(v, clink, irqp)
165 	pciintr_icu_handle_t v;
166 	int clink, *irqp;
167 {
168 	struct piix_handle *ph = v;
169 	int shift;
170 	pcireg_t reg;
171 
172 	if (PIIX_LEGAL_LINK(clink) == 0)
173 		return (1);
174 
175 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
176 	shift = clink << 3;
177 	if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)
178 		*irqp = I386_PCI_INTERRUPT_LINE_NO_CONNECTION;
179 	else
180 		*irqp = PIIX_PIRQ(reg, clink);
181 
182 	return (0);
183 }
184 
185 int
186 piix_set_intr(v, clink, irq)
187 	pciintr_icu_handle_t v;
188 	int clink, irq;
189 {
190 	struct piix_handle *ph = v;
191 	int shift;
192 	pcireg_t reg;
193 
194 	if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0)
195 		return (1);
196 
197 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
198 	shift = clink << 3;
199 	reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);
200 	reg |= irq << shift;
201 	pci_conf_write(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ, reg);
202 
203 	return (0);
204 }
205 
206 int
207 piix_get_trigger(v, irq, triggerp)
208 	pciintr_icu_handle_t v;
209 	int irq, *triggerp;
210 {
211 	struct piix_handle *ph = v;
212 	int off, bit;
213 	u_int8_t elcr;
214 
215 	if (PIIX_LEGAL_IRQ(irq) == 0)
216 		return (1);
217 
218 	off = (irq > 7) ? 1 : 0;
219 	bit = irq & 7;
220 
221 	elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
222 	if (elcr & (1 << bit))
223 		*triggerp = IST_LEVEL;
224 	else
225 		*triggerp = IST_EDGE;
226 
227 	return (0);
228 }
229 
230 int
231 piix_set_trigger(v, irq, trigger)
232 	pciintr_icu_handle_t v;
233 	int irq, trigger;
234 {
235 	struct piix_handle *ph = v;
236 	int off, bit;
237 	u_int8_t elcr;
238 
239 	if (PIIX_LEGAL_IRQ(irq) == 0)
240 		return (1);
241 
242 	off = (irq > 7) ? 1 : 0;
243 	bit = irq & 7;
244 
245 	elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
246 	if (trigger == IST_LEVEL)
247 		elcr |= (1 << bit);
248 	else
249 		elcr &= ~(1 << bit);
250 	bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr);
251 
252 	return (0);
253 }
254 
255 #ifdef PIIX_DEBUG
256 void
257 piix_pir_dump(ph)
258 	struct piix_handle *ph;
259 {
260 	int i, irq;
261 	pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
262 	u_int8_t elcr[2];
263 
264 	elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0);
265 	elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1);
266 
267 	for (i = 0; i < 4; i++) {
268 		irq = PIIX_PIRQ(irqs, i);
269 		if (irq & PIIX_CFG_PIRQ_NONE)
270 			printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq);
271 		else
272 			printf("PIIX PIRQ %d: irq %d\n", i, irq);
273 	}
274 	printf("PIIX irq:");
275 	for (i = 0; i < 16; i++)
276 		printf(" %2d", i);
277 	printf("\n");
278 	printf(" trigger:");
279 	for (i = 0; i < 16; i++)
280 		printf("  %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ?
281 		       'L' : 'E');
282 	printf("\n");
283 }
284 #endif /* PIIX_DEBUG */
285