1 /* $NetBSD: pci_intr_fixup.c,v 1.11 2001/01/05 18:39:12 aymeric Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * PCI Interrupt Router support. 67 */ 68 69 #include "opt_pcibios.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 #include <sys/device.h> 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/pci/pcireg.h> 82 #include <dev/pci/pcivar.h> 83 #include <dev/pci/pcidevs.h> 84 85 #include <i386/isa/icu.h> 86 #include <i386/pci/pci_intr_fixup.h> 87 #include <i386/pci/pcibios.h> 88 89 struct pciintr_link_map { 90 int link; 91 int clink; 92 int irq; 93 u_int16_t bitmap; 94 int fixup_stage; 95 SIMPLEQ_ENTRY(pciintr_link_map) list; 96 }; 97 98 pciintr_icu_tag_t pciintr_icu_tag = NULL; 99 pciintr_icu_handle_t pciintr_icu_handle; 100 101 #ifdef PCIBIOS_IRQS_HINT 102 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 103 #endif 104 105 struct pciintr_link_map *pciintr_link_lookup __P((int)); 106 struct pciintr_link_map *pciintr_link_alloc __P((struct pcibios_intr_routing *, 107 int)); 108 struct pcibios_intr_routing *pciintr_pir_lookup __P((int, int)); 109 static int pciintr_bitmap_count_irq __P((int, int *)); 110 static int pciintr_bitmap_find_lowest_irq __P((int, int *)); 111 int pciintr_link_init __P((void)); 112 #ifdef PCIBIOS_INTR_GUESS 113 int pciintr_guess_irq __P((void)); 114 #endif 115 int pciintr_link_fixup __P((void)); 116 int pciintr_link_route __P((u_int16_t *)); 117 int pciintr_irq_release __P((u_int16_t *)); 118 int pciintr_header_fixup __P((pci_chipset_tag_t)); 119 void pciintr_do_header_fixup __P((pci_chipset_tag_t, pcitag_t)); 120 121 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 122 123 const struct pciintr_icu_table { 124 pci_vendor_id_t piit_vendor; 125 pci_product_id_t piit_product; 126 int (*piit_init) __P((pci_chipset_tag_t, 127 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 128 pciintr_icu_handle_t *)); 129 } pciintr_icu_table[] = { 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 131 piix_init }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 133 piix_init }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 135 piix_init }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 137 piix_init }, 138 139 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 140 opti82c558_init }, 141 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 142 opti82c700_init }, 143 144 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 145 via82c586_init }, 146 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 147 via82c586_init }, 148 149 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 150 sis85c503_init }, 151 152 { 0, 0, 153 NULL }, 154 }; 155 156 const struct pciintr_icu_table *pciintr_icu_lookup __P((pcireg_t)); 157 158 const struct pciintr_icu_table * 159 pciintr_icu_lookup(id) 160 pcireg_t id; 161 { 162 const struct pciintr_icu_table *piit; 163 164 for (piit = pciintr_icu_table; 165 piit->piit_init != NULL; 166 piit++) { 167 if (PCI_VENDOR(id) == piit->piit_vendor && 168 PCI_PRODUCT(id) == piit->piit_product) 169 return (piit); 170 } 171 172 return (NULL); 173 } 174 175 struct pciintr_link_map * 176 pciintr_link_lookup(link) 177 int link; 178 { 179 struct pciintr_link_map *l; 180 181 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 182 l = SIMPLEQ_NEXT(l, list)) { 183 if (l->link == link) 184 return (l); 185 } 186 187 return (NULL); 188 } 189 190 struct pciintr_link_map * 191 pciintr_link_alloc(pir, pin) 192 struct pcibios_intr_routing *pir; 193 int pin; 194 { 195 int link = pir->linkmap[pin].link, clink, irq; 196 struct pciintr_link_map *l, *lstart; 197 198 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 199 /* 200 * Get the canonical link value for this entry. 201 */ 202 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 203 link, &clink) != 0) { 204 /* 205 * ICU doesn't understand the link value. 206 * Just ignore this PIR entry. 207 */ 208 #ifdef DIAGNOSTIC 209 printf("pciintr_link_alloc: bus %d device %d: " 210 "link 0x%02x invalid\n", 211 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link); 212 #endif 213 return (NULL); 214 } 215 216 /* 217 * Check the link value by asking the ICU for the 218 * canonical link value. 219 * Also, determine if this PIRQ is mapped to an IRQ. 220 */ 221 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 222 clink, &irq) != 0) { 223 /* 224 * ICU doesn't understand the canonical link value. 225 * Just ignore this PIR entry. 226 */ 227 #ifdef DIAGNOSTIC 228 printf("pciintr_link_alloc: " 229 "bus %d device %d link 0x%02x: " 230 "PIRQ 0x%02x invalid\n", 231 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link, 232 clink); 233 #endif 234 return (NULL); 235 } 236 } 237 238 l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT); 239 if (l == NULL) 240 panic("pciintr_link_alloc"); 241 242 memset(l, 0, sizeof(*l)); 243 244 l->link = link; 245 l->bitmap = pir->linkmap[pin].bitmap; 246 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 247 l->clink = clink; 248 l->irq = irq; /* maybe I386_PCI_INTERRUPT_LINE_NO_CONNECTION */ 249 } else { 250 l->clink = link; /* only for PCIBIOSVERBOSE diagnostic */ 251 l->irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 252 } 253 254 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 255 if (lstart == NULL || lstart->link < l->link) 256 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 257 else 258 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 259 260 return (l); 261 } 262 263 struct pcibios_intr_routing * 264 pciintr_pir_lookup(bus, device) 265 int bus, device; 266 { 267 struct pcibios_intr_routing *pir; 268 int entry; 269 270 if (pcibios_pir_table == NULL) 271 return (NULL); 272 273 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 274 pir = &pcibios_pir_table[entry]; 275 if (pir->bus == bus && 276 PIR_DEVFUNC_DEVICE(pir->device) == device) 277 return (pir); 278 } 279 280 return (NULL); 281 } 282 283 static int 284 pciintr_bitmap_count_irq(irq_bitmap, irqp) 285 int irq_bitmap, *irqp; 286 { 287 int i, bit, count = 0, irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 288 289 if (irq_bitmap != 0) { 290 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 291 if (irq_bitmap & bit) { 292 irq = i; 293 count++; 294 } 295 } 296 } 297 *irqp = irq; 298 return (count); 299 } 300 301 static int 302 pciintr_bitmap_find_lowest_irq(irq_bitmap, irqp) 303 int irq_bitmap, *irqp; 304 { 305 int i, bit; 306 307 if (irq_bitmap != 0) { 308 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 309 if (irq_bitmap & bit) { 310 *irqp = i; 311 return (1); /* found */ 312 } 313 } 314 } 315 return (0); /* not found */ 316 } 317 318 int 319 pciintr_link_init() 320 { 321 int entry, pin, link; 322 struct pcibios_intr_routing *pir; 323 struct pciintr_link_map *l; 324 325 if (pcibios_pir_table == NULL) { 326 /* No PIR table; can't do anything. */ 327 printf("pciintr_link_init: no PIR table\n"); 328 return (1); 329 } 330 331 SIMPLEQ_INIT(&pciintr_link_map_list); 332 333 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 334 pir = &pcibios_pir_table[entry]; 335 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 336 link = pir->linkmap[pin].link; 337 if (link == 0) { 338 /* No connection for this pin. */ 339 continue; 340 } 341 /* 342 * Multiple devices may be wired to the same 343 * interrupt; check to see if we've seen this 344 * one already. If not, allocate a new link 345 * map entry and stuff it in the map. 346 */ 347 l = pciintr_link_lookup(link); 348 if (l == NULL) { 349 (void) pciintr_link_alloc(pir, pin); 350 } else if (pir->linkmap[pin].bitmap != l->bitmap) { 351 /* 352 * violates PCI IRQ Routing Table Specification 353 */ 354 #ifdef DIAGNOSTIC 355 printf("pciintr_link_init: " 356 "bus %d device %d link 0x%02x: " 357 "bad irq bitmap 0x%04x, " 358 "should be 0x%04x\n", 359 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), 360 link, pir->linkmap[pin].bitmap, l->bitmap); 361 #endif 362 /* safer value. */ 363 l->bitmap &= pir->linkmap[pin].bitmap; 364 /* XXX - or, should ignore this entry? */ 365 } 366 } 367 } 368 369 return (0); 370 } 371 372 #ifdef PCIBIOS_INTR_GUESS 373 /* 374 * No compatible PCI ICU found. 375 * Hopes the BIOS already setup the ICU. 376 */ 377 int 378 pciintr_guess_irq() 379 { 380 struct pciintr_link_map *l; 381 int irq, guessed = 0; 382 383 /* 384 * Stage 1: If only one IRQ is available for the link, use it. 385 */ 386 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 387 l = SIMPLEQ_NEXT(l, list)) { 388 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 389 continue; 390 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 391 l->irq = irq; 392 l->fixup_stage = 1; 393 #ifdef PCIINTR_DEBUG 394 printf("pciintr_guess_irq (stage 1): " 395 "guessing PIRQ 0x%02x to be IRQ %d\n", 396 l->clink, l->irq); 397 #endif 398 guessed = 1; 399 } 400 } 401 402 return (guessed ? 0 : -1); 403 } 404 #endif /* PCIBIOS_INTR_GUESS */ 405 406 int 407 pciintr_link_fixup() 408 { 409 struct pciintr_link_map *l; 410 int irq; 411 u_int16_t pciirq = 0; 412 413 /* 414 * First stage: Attempt to connect PIRQs which aren't 415 * yet connected. 416 */ 417 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 418 l = SIMPLEQ_NEXT(l, list)) { 419 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 420 /* 421 * Interrupt is already connected. Don't do 422 * anything to it. 423 * In this case, l->fixup_stage == 0. 424 */ 425 pciirq |= 1 << l->irq; 426 #ifdef PCIINTR_DEBUG 427 printf("pciintr_link_fixup: PIRQ 0x%02x already " 428 "connected to IRQ %d\n", l->clink, l->irq); 429 #endif 430 continue; 431 } 432 /* 433 * Interrupt isn't connected. Attempt to assign it to an IRQ. 434 */ 435 #ifdef PCIINTR_DEBUG 436 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 437 l->clink); 438 #endif 439 /* 440 * Just do the easy case now; we'll defer the harder ones 441 * to Stage 2. 442 */ 443 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 444 l->irq = irq; 445 l->fixup_stage = 1; 446 pciirq |= 1 << irq; 447 #ifdef PCIINTR_DEBUG 448 printf(", assigning IRQ %d", l->irq); 449 #endif 450 } 451 #ifdef PCIINTR_DEBUG 452 printf("\n"); 453 #endif 454 } 455 456 /* 457 * Stage 2: Attempt to connect PIRQs which we didn't 458 * connect in Stage 1. 459 */ 460 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 461 l = SIMPLEQ_NEXT(l, list)) { 462 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 463 continue; 464 if (pciintr_bitmap_find_lowest_irq(l->bitmap & pciirq, 465 &l->irq)) { 466 /* 467 * This IRQ is a valid PCI IRQ already 468 * connected to another PIRQ, and also an 469 * IRQ our PIRQ can use; connect it up! 470 */ 471 l->fixup_stage = 2; 472 #ifdef PCIINTR_DEBUG 473 printf("pciintr_link_fixup (stage 2): " 474 "assigning IRQ %d to PIRQ 0x%02x\n", 475 l->irq, l->clink); 476 #endif 477 } 478 } 479 480 #ifdef PCIBIOS_IRQS_HINT 481 /* 482 * Stage 3: The worst case. I need configuration hint that 483 * user supplied a mask for the PCI irqs 484 */ 485 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 486 l = SIMPLEQ_NEXT(l, list)) { 487 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 488 continue; 489 if (pciintr_bitmap_find_lowest_irq( 490 l->bitmap & pcibios_irqs_hint, &l->irq)) { 491 l->fixup_stage = 3; 492 #ifdef PCIINTR_DEBUG 493 printf("pciintr_link_fixup (stage 3): " 494 "assigning IRQ %d to PIRQ 0x%02x\n", 495 l->irq, l->clink); 496 #endif 497 } 498 } 499 #endif /* PCIBIOS_IRQS_HINT */ 500 501 return (0); 502 } 503 504 int 505 pciintr_link_route(pciirq) 506 u_int16_t *pciirq; 507 { 508 struct pciintr_link_map *l; 509 int rv = 0; 510 511 *pciirq = 0; 512 513 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 514 l = SIMPLEQ_NEXT(l, list)) { 515 if (l->fixup_stage == 0) { 516 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 517 /* Appropriate interrupt was not found. */ 518 #ifdef DIAGNOSTIC 519 printf("pciintr_link_route: " 520 "PIRQ 0x%02x: no IRQ, try " 521 "\"options PCIBIOS_IRQS_HINT=0x%04x\"\n", 522 l->clink, 523 /* suggest irq 9/10/11, if possible */ 524 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 525 : l->bitmap); 526 #endif 527 } else { 528 /* BIOS setting has no problem */ 529 #ifdef PCIINTR_DEBUG 530 printf("pciintr_link_route: " 531 "route of PIRQ 0x%02x -> " 532 "IRQ %d preserved BIOS setting\n", 533 l->clink, l->irq); 534 #endif 535 *pciirq |= (1 << l->irq); 536 } 537 continue; /* nothing to do. */ 538 } 539 540 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 541 l->clink, l->irq) != 0 || 542 pciintr_icu_set_trigger(pciintr_icu_tag, 543 pciintr_icu_handle, 544 l->irq, IST_LEVEL) != 0) { 545 printf("pciintr_link_route: route of PIRQ 0x%02x -> " 546 "IRQ %d failed\n", l->clink, l->irq); 547 rv = 1; 548 } else { 549 /* 550 * Succssfully routed interrupt. Mark this as 551 * a PCI interrupt. 552 */ 553 *pciirq |= (1 << l->irq); 554 } 555 } 556 557 return (rv); 558 } 559 560 int 561 pciintr_irq_release(pciirq) 562 u_int16_t *pciirq; 563 { 564 int i, bit; 565 566 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 567 if ((*pciirq & bit) == 0) 568 (void) pciintr_icu_set_trigger(pciintr_icu_tag, 569 pciintr_icu_handle, i, IST_EDGE); 570 } 571 572 return (0); 573 } 574 575 int 576 pciintr_header_fixup(pc) 577 pci_chipset_tag_t pc; 578 { 579 PCIBIOS_PRINTV(("------------------------------------------\n")); 580 PCIBIOS_PRINTV((" device vendor product pin PIRQ IRQ stage\n")); 581 PCIBIOS_PRINTV(("------------------------------------------\n")); 582 pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup); 583 PCIBIOS_PRINTV(("------------------------------------------\n")); 584 585 return (0); 586 } 587 588 void 589 pciintr_do_header_fixup(pc, tag) 590 pci_chipset_tag_t pc; 591 pcitag_t tag; 592 { 593 struct pcibios_intr_routing *pir; 594 struct pciintr_link_map *l; 595 int pin, irq, link; 596 int bus, device, function; 597 pcireg_t intr, id; 598 599 pci_decompose_tag(pc, tag, &bus, &device, &function); 600 id = pci_conf_read(pc, tag, PCI_ID_REG); 601 602 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 603 pin = PCI_INTERRUPT_PIN(intr); 604 irq = PCI_INTERRUPT_LINE(intr); 605 606 if (pin == 0) { 607 /* 608 * No interrupt used. 609 */ 610 return; 611 } 612 613 pir = pciintr_pir_lookup(bus, device); 614 if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) { 615 /* 616 * Interrupt not connected; no 617 * need to change. 618 */ 619 return; 620 } 621 622 l = pciintr_link_lookup(link); 623 if (l == NULL) { 624 #ifdef PCIINTR_DEBUG 625 /* 626 * No link map entry. 627 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 628 * was failed. 629 */ 630 printf("pciintr_header_fixup: no entry for link 0x%02x " 631 "(%d:%d:%d:%c)\n", link, bus, device, function, 632 '@' + pin); 633 #endif 634 return; 635 } 636 637 #ifdef PCIBIOSVERBOSE 638 if (pcibiosverbose) { 639 printf("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x", 640 bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id), 641 '@' + pin, l->clink); 642 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 643 printf(" -"); 644 else 645 printf(" %3d", l->irq); 646 printf(" %d ", l->fixup_stage); 647 } 648 #endif 649 650 /* 651 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 652 * with them. 653 */ 654 if (irq == 14 || irq == 15) { 655 PCIBIOS_PRINTV((" WARNING: ignored\n")); 656 return; 657 } 658 659 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 660 /* Appropriate interrupt was not found. */ 661 if (pciintr_icu_tag == NULL && 662 irq != 0 && irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 663 /* 664 * Do not print warning, 665 * if no compatible PCI ICU found, 666 * but the irq is already assigned by BIOS. 667 */ 668 PCIBIOS_PRINTV(("\n")); 669 } else { 670 PCIBIOS_PRINTV((" WARNING: missing IRQ\n")); 671 } 672 return; 673 } 674 675 if (l->irq == irq) { 676 /* don't have to reconfigure */ 677 PCIBIOS_PRINTV((" already assigned\n")); 678 return; 679 } 680 681 if (irq == 0 || irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 682 PCIBIOS_PRINTV((" fixed up\n")); 683 } else { 684 /* routed by BIOS, but inconsistent */ 685 #ifdef PCIBIOS_INTR_FIXUP_FORCE 686 /* believe PCI IRQ Routing table */ 687 PCIBIOS_PRINTV((" WARNING: overriding irq %d\n", irq)); 688 #else 689 /* believe PCI Interrupt Configuration Register (default) */ 690 PCIBIOS_PRINTV((" WARNING: preserving irq %d\n", irq)); 691 return; 692 #endif 693 } 694 695 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 696 intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT); 697 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 698 } 699 700 int 701 pci_intr_fixup(pc, iot, pciirq) 702 pci_chipset_tag_t pc; 703 bus_space_tag_t iot; 704 u_int16_t *pciirq; 705 { 706 const struct pciintr_icu_table *piit = NULL; 707 pcitag_t icutag; 708 pcireg_t icuid; 709 710 /* 711 * Attempt to initialize our PCI interrupt router. If 712 * the PIR Table is present in ROM, use the location 713 * specified by the PIR Table, and use the compat ID, 714 * if present. Otherwise, we have to look for the router 715 * ourselves (the PCI-ISA bridge). 716 */ 717 if (pcibios_pir_header.signature != 0) { 718 icutag = pci_make_tag(pc, pcibios_pir_header.router_bus, 719 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 720 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 721 icuid = pcibios_pir_header.compat_router; 722 if (icuid == 0 || 723 (piit = pciintr_icu_lookup(icuid)) == NULL) { 724 /* 725 * No compat ID, or don't know the compat ID? Read 726 * it from the configuration header. 727 */ 728 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 729 } 730 if (piit == NULL) 731 piit = pciintr_icu_lookup(icuid); 732 } else { 733 int device, maxdevs = pci_bus_maxdevs(pc, 0); 734 735 /* 736 * Search configuration space for a known interrupt 737 * router. 738 */ 739 for (device = 0; device < maxdevs; device++) { 740 icutag = pci_make_tag(pc, 0, device, 0); 741 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 742 743 /* Invalid vendor ID value? */ 744 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 745 continue; 746 /* XXX Not invalid, but we've done this ~forever. */ 747 if (PCI_VENDOR(icuid) == 0) 748 continue; 749 750 piit = pciintr_icu_lookup(icuid); 751 if (piit != NULL) 752 break; 753 } 754 } 755 756 if (piit == NULL) { 757 printf("pci_intr_fixup: no compatible PCI ICU found"); 758 if (pcibios_pir_header.signature != 0 && icuid != 0) 759 printf(": ICU vendor 0x%04x product 0x%04x", 760 PCI_VENDOR(icuid), PCI_PRODUCT(icuid)); 761 printf("\n"); 762 #ifdef PCIBIOS_INTR_GUESS 763 if (pciintr_link_init()) 764 return (-1); /* non-fatal */ 765 if (pciintr_guess_irq()) 766 return (-1); /* non-fatal */ 767 if (pciintr_header_fixup(pc)) 768 return (1); /* fatal */ 769 return (0); /* success! */ 770 #else 771 return (-1); /* non-fatal */ 772 #endif 773 } 774 775 /* 776 * Initialize the PCI ICU. 777 */ 778 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 779 &pciintr_icu_handle) != 0) 780 return (-1); /* non-fatal */ 781 782 /* 783 * Initialize the PCI interrupt link map. 784 */ 785 if (pciintr_link_init()) 786 return (-1); /* non-fatal */ 787 788 /* 789 * Fix up the link->IRQ mappings. 790 */ 791 if (pciintr_link_fixup() != 0) 792 return (-1); /* non-fatal */ 793 794 /* 795 * Now actually program the PCI ICU with the new 796 * routing information. 797 */ 798 if (pciintr_link_route(pciirq) != 0) 799 return (1); /* fatal */ 800 801 /* 802 * Now that we've routed all of the PIRQs, rewrite the PCI 803 * configuration headers to reflect the new mapping. 804 */ 805 if (pciintr_header_fixup(pc) != 0) 806 return (1); /* fatal */ 807 808 /* 809 * Free any unused PCI IRQs for ISA devices. 810 */ 811 if (pciintr_irq_release(pciirq) != 0) 812 return (-1); /* non-fatal */ 813 814 /* 815 * All done! 816 */ 817 return (0); /* success! */ 818 } 819