1 /* $NetBSD: gscpcib.c,v 1.19 2021/04/24 23:36:39 thorpej Exp $ */ 2 /* $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $ */ 3 /* 4 * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge 21 * that attaches instead of pcib(4). In addition to the core pcib(4) 22 * functionality this driver provides support for the GPIO interface. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: gscpcib.c,v 1.19 2021/04/24 23:36:39 thorpej Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/device.h> 31 #include <sys/gpio.h> 32 #include <sys/kernel.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 40 #include <dev/gpio/gpiovar.h> 41 42 #include <i386/pci/gscpcibreg.h> 43 #include <arch/x86/pci/pcibvar.h> 44 45 #include "gpio.h" 46 47 struct gscpcib_softc { 48 struct pcib_softc sc_pcib; 49 50 bool sc_gpio_present; 51 device_t sc_gpiobus; 52 53 /* GPIO interface */ 54 bus_space_tag_t sc_gpio_iot; 55 bus_space_handle_t sc_gpio_ioh; 56 struct gpio_chipset_tag sc_gpio_gc; 57 gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS]; 58 }; 59 60 int gscpcib_match(device_t, cfdata_t, void *); 61 void gscpcib_attach(device_t, device_t, void *); 62 int gscpcib_detach(device_t, int); 63 int gscpcib_rescan(device_t, const char *, const int *); 64 void gscpcib_childdetached(device_t, device_t); 65 66 int gscpcib_gpio_pin_read(void *, int); 67 void gscpcib_gpio_pin_write(void *, int, int); 68 void gscpcib_gpio_pin_ctl(void *, int, int); 69 70 CFATTACH_DECL3_NEW(gscpcib, sizeof(struct gscpcib_softc), 71 gscpcib_match, gscpcib_attach, gscpcib_detach, NULL, gscpcib_rescan, 72 gscpcib_childdetached, DVF_DETACH_SHUTDOWN); 73 74 extern struct cfdriver gscpcib_cd; 75 76 void 77 gscpcib_childdetached(device_t self, device_t child) 78 { 79 struct gscpcib_softc *sc = device_private(self); 80 81 if (sc->sc_gpiobus == child) 82 sc->sc_gpiobus = NULL; 83 else 84 pcibchilddet(self, child); 85 } 86 87 int 88 gscpcib_rescan(device_t self, const char *ifattr, const int *loc) 89 { 90 #if NGPIO > 0 91 struct gscpcib_softc *sc = device_private(self); 92 93 /* Attach GPIO framework */ 94 if (sc->sc_gpio_present && ifattr_match(ifattr, "gpiobus") && 95 sc->sc_gpiobus == NULL) { 96 struct gpiobus_attach_args gba; 97 98 gba.gba_gc = &sc->sc_gpio_gc; 99 gba.gba_pins = sc->sc_gpio_pins; 100 gba.gba_npins = GSCGPIO_NPINS; 101 102 sc->sc_gpiobus = config_found(self, &gba, gpiobus_print, 103 CFARG_IATTR, "gpiobus", 104 CFARG_EOL); 105 return 0; 106 } 107 #endif 108 109 return pcibrescan(self, ifattr, loc); 110 } 111 112 int 113 gscpcib_match(device_t parent, cfdata_t match, void *aux) 114 { 115 struct pci_attach_args *pa = aux; 116 117 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 118 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 119 return (0); 120 121 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 122 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA) 123 return (2); /* supersede pcib(4) */ 124 125 return (0); 126 } 127 128 void 129 gscpcib_attach(device_t parent, device_t self, void *aux) 130 { 131 struct gscpcib_softc *sc = device_private(self); 132 struct pci_attach_args *pa = aux; 133 pcireg_t gpiobase; 134 int i; 135 136 /* Map GPIO I/O space */ 137 gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE); 138 sc->sc_gpio_iot = pa->pa_iot; 139 if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase), 140 GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) { 141 printf(": failed to map GPIO I/O space"); 142 goto corepcib; 143 } 144 145 /* Initialize pins array */ 146 for (i = 0; i < GSCGPIO_NPINS; i++) { 147 sc->sc_gpio_pins[i].pin_num = i; 148 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 149 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 150 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 151 GPIO_PIN_PULLUP; 152 153 /* safe defaults */ 154 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE; 155 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW; 156 gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags); 157 gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state); 158 } 159 160 /* Create controller tag */ 161 sc->sc_gpio_gc.gp_cookie = sc; 162 sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read; 163 sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write; 164 sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl; 165 166 sc->sc_gpio_present = true; 167 168 corepcib: 169 /* Provide core pcib(4) functionality */ 170 pcibattach(parent, self, aux); 171 172 gscpcib_rescan(self, "gpiobus", NULL); 173 } 174 175 int 176 gscpcib_detach(device_t self, int flags) 177 { 178 int rc; 179 struct gscpcib_softc *sc = device_private(self); 180 181 if ((rc = config_detach_children(self, flags)) != 0) 182 return rc; 183 184 if ((rc = pcibdetach(self, flags)) != 0) 185 return rc; 186 187 if (sc->sc_gpio_present) 188 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SIZE); 189 190 return rc; 191 } 192 193 static inline void 194 gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin) 195 { 196 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin); 197 } 198 199 int 200 gscpcib_gpio_pin_read(void *arg, int pin) 201 { 202 struct gscpcib_softc *sc = arg; 203 int reg, shift; 204 uint32_t data; 205 206 reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1); 207 shift = pin % 32; 208 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 209 210 return ((data >> shift) & 0x1); 211 } 212 213 void 214 gscpcib_gpio_pin_write(void *arg, int pin, int value) 215 { 216 struct gscpcib_softc *sc = arg; 217 int reg, shift; 218 uint32_t data; 219 220 reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1); 221 shift = pin % 32; 222 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 223 if (value == 0) 224 data &= ~(1 << shift); 225 else if (value == 1) 226 data |= (1 << shift); 227 228 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 229 } 230 231 void 232 gscpcib_gpio_pin_ctl(void *arg, int pin, int flags) 233 { 234 struct gscpcib_softc *sc = arg; 235 uint32_t conf; 236 237 gscpcib_gpio_pin_select(sc, pin); 238 conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 239 GSCGPIO_CONF); 240 241 conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL | 242 GSCGPIO_CONF_PULLUP); 243 if ((flags & GPIO_PIN_TRISTATE) == 0) 244 conf |= GSCGPIO_CONF_OUTPUTEN; 245 if (flags & GPIO_PIN_PUSHPULL) 246 conf |= GSCGPIO_CONF_PUSHPULL; 247 if (flags & GPIO_PIN_PULLUP) 248 conf |= GSCGPIO_CONF_PULLUP; 249 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 250 GSCGPIO_CONF, conf); 251 } 252