1 /* $NetBSD: glxsb.c,v 1.14 2016/07/14 10:19:05 msaitoh Exp $ */ 2 /* $OpenBSD: glxsb.c,v 1.7 2007/02/12 14:31:45 tom Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org> 6 * Copyright (c) 2003, 2004 Theo de Raadt 7 * Copyright (c) 2003 Jason Wright 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for the security block on the AMD Geode LX processors 24 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: glxsb.c,v 1.14 2016/07/14 10:19:05 msaitoh Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/device.h> 33 #include <sys/malloc.h> 34 #include <sys/mbuf.h> 35 #include <sys/types.h> 36 #include <sys/callout.h> 37 #include <sys/bus.h> 38 #include <sys/cprng.h> 39 #include <sys/rndsource.h> 40 41 #include <machine/cpufunc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <opencrypto/cryptodev.h> 47 #include <crypto/rijndael/rijndael.h> 48 49 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */ 50 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */ 51 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */ 52 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */ 53 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */ 54 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */ 55 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */ 56 57 /* For GLD_MSR_CTRL: */ 58 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */ 59 #define SB_GMC_DIV1 0x0001 60 #define SB_GMC_DIV2 0x0002 61 #define SB_GMC_DIV3 0x0003 62 #define SB_GMC_DIV_MASK 0x0003 63 #define SB_GMC_SBI 0x0004 /* AES swap bits */ 64 #define SB_GMC_SBY 0x0008 /* AES swap bytes */ 65 #define SB_GMC_TW 0x0010 /* Time write (EEPROM) */ 66 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */ 67 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */ 68 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */ 69 #define SB_GMC_T_SEL3 0x0300 /* RNG LFSR+whitener */ 70 #define SB_GMC_T_SEL_MASK 0x0300 71 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */ 72 #define SB_GMC_T_TM 0x0800 /* RNG test mode */ 73 /* (deterministic) */ 74 75 /* Security Block configuration/control registers (offsets from base) */ 76 77 #define SB_CTL_A 0x0000 /* RW - SB Control A */ 78 #define SB_CTL_B 0x0004 /* RW - SB Control B */ 79 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */ 80 #define SB_SOURCE_A 0x0010 /* RW - Source A */ 81 #define SB_DEST_A 0x0014 /* RW - Destination A */ 82 #define SB_LENGTH_A 0x0018 /* RW - Length A */ 83 #define SB_SOURCE_B 0x0020 /* RW - Source B */ 84 #define SB_DEST_B 0x0024 /* RW - Destination B */ 85 #define SB_LENGTH_B 0x0028 /* RW - Length B */ 86 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */ 87 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */ 88 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */ 89 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */ 90 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */ 91 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */ 92 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */ 93 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */ 94 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */ 95 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */ 96 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */ 97 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */ 98 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */ 99 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */ 100 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */ 101 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */ 102 103 /* For SB_CTL_A and _B */ 104 #define SB_CTL_ST 0x0001 /* Start operation (enc/dec) */ 105 #define SB_CTL_ENC 0x0002 /* Encrypt (0 is decrypt) */ 106 #define SB_CTL_DEC 0x0000 /* Decrypt */ 107 #define SB_CTL_WK 0x0004 /* Use writable key (we set) */ 108 #define SB_CTL_DC 0x0008 /* Destination coherent */ 109 #define SB_CTL_SC 0x0010 /* Source coherent */ 110 #define SB_CTL_CBC 0x0020 /* CBC (0 is ECB) */ 111 112 /* For SB_AES_INT */ 113 #define SB_AI_DISABLE_AES_A 0x0001 /* Disable AES A compl int */ 114 #define SB_AI_ENABLE_AES_A 0x0000 /* Enable AES A compl int */ 115 #define SB_AI_DISABLE_AES_B 0x0002 /* Disable AES B compl int */ 116 #define SB_AI_ENABLE_AES_B 0x0000 /* Enable AES B compl int */ 117 #define SB_AI_DISABLE_EEPROM 0x0004 /* Disable EEPROM op comp int */ 118 #define SB_AI_ENABLE_EEPROM 0x0000 /* Enable EEPROM op compl int */ 119 #define SB_AI_AES_A_COMPLETE 0x0100 /* AES A operation complete */ 120 #define SB_AI_AES_B_COMPLETE 0x0200 /* AES B operation complete */ 121 #define SB_AI_EEPROM_COMPLETE 0x0400 /* EEPROM operation complete */ 122 123 #define SB_RNS_TRNG_VALID 0x0001 /* in SB_RANDOM_NUM_STATUS */ 124 125 #define SB_MEM_SIZE 0x0810 /* Size of memory block */ 126 127 #define SB_AES_ALIGN 0x0010 /* Source and dest buffers */ 128 /* must be 16-byte aligned */ 129 #define SB_AES_BLOCK_SIZE 0x0010 130 131 /* 132 * The Geode LX security block AES acceleration doesn't perform scatter- 133 * gather: it just takes source and destination addresses. Therefore the 134 * plain- and ciphertexts need to be contiguous. To this end, we allocate 135 * a buffer for both, and accept the overhead of copying in and out. If 136 * the number of bytes in one operation is bigger than allowed for by the 137 * buffer (buffer is twice the size of the max length, as it has both input 138 * and output) then we have to perform multiple encryptions/decryptions. 139 */ 140 #define GLXSB_MAX_AES_LEN 16384 141 142 struct glxsb_dma_map { 143 bus_dmamap_t dma_map; 144 bus_dma_segment_t dma_seg; 145 int dma_nsegs; 146 int dma_size; 147 void * dma_vaddr; 148 uint32_t dma_paddr; 149 }; 150 struct glxsb_session { 151 uint32_t ses_key[4]; 152 uint8_t ses_iv[SB_AES_BLOCK_SIZE]; 153 int ses_klen; 154 int ses_used; 155 }; 156 157 struct glxsb_softc { 158 device_t sc_dev; 159 bus_space_tag_t sc_iot; 160 bus_space_handle_t sc_ioh; 161 struct callout sc_co; 162 163 bus_dma_tag_t sc_dmat; 164 struct glxsb_dma_map sc_dma; 165 int32_t sc_cid; 166 int sc_nsessions; 167 struct glxsb_session *sc_sessions; 168 169 krndsource_t sc_rnd_source; 170 }; 171 172 int glxsb_match(device_t, cfdata_t, void *); 173 void glxsb_attach(device_t, device_t, void *); 174 void glxsb_rnd(void *); 175 176 CFATTACH_DECL_NEW(glxsb, sizeof(struct glxsb_softc), 177 glxsb_match, glxsb_attach, NULL, NULL); 178 179 #define GLXSB_SESSION(sid) ((sid) & 0x0fffffff) 180 #define GLXSB_SID(crd,ses) (((crd) << 28) | ((ses) & 0x0fffffff)) 181 182 int glxsb_crypto_setup(struct glxsb_softc *); 183 int glxsb_crypto_newsession(void *, uint32_t *, struct cryptoini *); 184 int glxsb_crypto_process(void *, struct cryptop *, int); 185 int glxsb_crypto_freesession(void *, uint64_t); 186 static __inline void glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t, 187 uint32_t, void *, int, void *); 188 189 int glxsb_dma_alloc(struct glxsb_softc *, int, struct glxsb_dma_map *); 190 void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *); 191 void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *); 192 void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *); 193 194 int 195 glxsb_match(device_t parent, cfdata_t match, void *aux) 196 { 197 struct pci_attach_args *pa = aux; 198 199 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 200 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_GEODELX_AES) 201 return (1); 202 203 return (0); 204 } 205 206 void 207 glxsb_attach(device_t parent, device_t self, void *aux) 208 { 209 struct glxsb_softc *sc = device_private(self); 210 struct pci_attach_args *pa = aux; 211 bus_addr_t membase; 212 bus_size_t memsize; 213 uint64_t msr; 214 uint32_t intr; 215 216 msr = rdmsr(SB_GLD_MSR_CAP); 217 if ((msr & 0xFFFF00) != 0x130400) { 218 aprint_error(": unknown ID 0x%x\n", 219 (int)((msr & 0xFFFF00) >> 16)); 220 return; 221 } 222 223 /* printf(": revision %d", (int) (msr & 0xFF)); */ 224 225 /* Map in the security block configuration/control registers */ 226 if (pci_mapreg_map(pa, PCI_MAPREG_START, 227 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->sc_iot, &sc->sc_ioh, &membase, &memsize)) { 229 aprint_error(": can't find mem space\n"); 230 return; 231 } 232 233 sc->sc_dev = self; 234 235 /* 236 * Configure the Security Block. 237 * 238 * We want to enable the noise generator (T_NE), and enable the 239 * linear feedback shift register and whitener post-processing 240 * (T_SEL = 3). Also ensure that test mode (deterministic values) 241 * is disabled. 242 */ 243 msr = rdmsr(SB_GLD_MSR_CTRL); 244 msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK); 245 msr |= SB_GMC_T_NE | SB_GMC_T_SEL3; 246 #if 0 247 msr |= SB_GMC_SBI | SB_GMC_SBY; /* for AES, if necessary */ 248 #endif 249 wrmsr(SB_GLD_MSR_CTRL, msr); 250 251 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), 252 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE); 253 254 /* Install a periodic collector for the "true" (AMD's word) RNG */ 255 callout_init(&sc->sc_co, 0); 256 callout_setfunc(&sc->sc_co, glxsb_rnd, sc); 257 glxsb_rnd(sc); 258 aprint_normal(": RNG"); 259 260 /* We don't have an interrupt handler, so disable completion INTs */ 261 intr = SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B | 262 SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE | 263 SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE; 264 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_AES_INT, intr); 265 266 sc->sc_dmat = pa->pa_dmat; 267 268 if (glxsb_crypto_setup(sc)) 269 aprint_normal(" AES"); 270 271 aprint_normal("\n"); 272 } 273 274 void 275 glxsb_rnd(void *v) 276 { 277 struct glxsb_softc *sc = v; 278 uint32_t status, value; 279 extern int hz; 280 281 status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM_STATUS); 282 if (status & SB_RNS_TRNG_VALID) { 283 value = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM); 284 rnd_add_data(&sc->sc_rnd_source, &value, sizeof(value), 285 sizeof(value) * NBBY); 286 } 287 288 callout_schedule(&sc->sc_co, (hz > 100) ? (hz / 100) : 1); 289 } 290 291 int 292 glxsb_crypto_setup(struct glxsb_softc *sc) 293 { 294 295 /* Allocate a contiguous DMA-able buffer to work in */ 296 if (glxsb_dma_alloc(sc, GLXSB_MAX_AES_LEN * 2, &sc->sc_dma) != 0) 297 return 0; 298 299 sc->sc_cid = crypto_get_driverid(0); 300 if (sc->sc_cid < 0) 301 return 0; 302 303 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 304 glxsb_crypto_newsession, glxsb_crypto_freesession, 305 glxsb_crypto_process, sc); 306 307 sc->sc_nsessions = 0; 308 309 return 1; 310 } 311 312 int 313 glxsb_crypto_newsession(void *aux, uint32_t *sidp, struct cryptoini *cri) 314 { 315 struct glxsb_softc *sc = aux; 316 struct glxsb_session *ses = NULL; 317 int sesn; 318 319 if (sc == NULL || sidp == NULL || cri == NULL || 320 cri->cri_next != NULL || cri->cri_alg != CRYPTO_AES_CBC || 321 cri->cri_klen != 128) 322 return (EINVAL); 323 324 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 325 if (sc->sc_sessions[sesn].ses_used == 0) { 326 ses = &sc->sc_sessions[sesn]; 327 break; 328 } 329 } 330 331 if (ses == NULL) { 332 sesn = sc->sc_nsessions; 333 ses = malloc((sesn + 1) * sizeof(*ses), M_DEVBUF, M_NOWAIT); 334 if (ses == NULL) 335 return (ENOMEM); 336 if (sesn != 0) { 337 memcpy(ses, sc->sc_sessions, sesn * sizeof(*ses)); 338 memset(sc->sc_sessions, 0, sesn * sizeof(*ses)); 339 free(sc->sc_sessions, M_DEVBUF); 340 } 341 sc->sc_sessions = ses; 342 ses = &sc->sc_sessions[sesn]; 343 sc->sc_nsessions++; 344 } 345 346 memset(ses, 0, sizeof(*ses)); 347 ses->ses_used = 1; 348 349 cprng_fast(ses->ses_iv, sizeof(ses->ses_iv)); 350 ses->ses_klen = cri->cri_klen; 351 352 /* Copy the key (Geode LX wants the primary key only) */ 353 memcpy(ses->ses_key, cri->cri_key, sizeof(ses->ses_key)); 354 355 *sidp = GLXSB_SID(0, sesn); 356 return (0); 357 } 358 359 int 360 glxsb_crypto_freesession(void *aux, uint64_t tid) 361 { 362 struct glxsb_softc *sc = aux; 363 int sesn; 364 uint32_t sid = ((uint32_t)tid) & 0xffffffff; 365 366 if (sc == NULL) 367 return (EINVAL); 368 sesn = GLXSB_SESSION(sid); 369 if (sesn >= sc->sc_nsessions) 370 return (EINVAL); 371 memset(&sc->sc_sessions[sesn], 0, sizeof(sc->sc_sessions[sesn])); 372 return (0); 373 } 374 375 /* 376 * Must be called at splnet() or higher 377 */ 378 static __inline void 379 glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc, 380 uint32_t pdst, void *key, int len, void *iv) 381 { 382 uint32_t status; 383 int i; 384 385 if (len & 0xF) { 386 printf("%s: len must be a multiple of 16 (not %d)\n", 387 device_xname(sc->sc_dev), len); 388 return; 389 } 390 391 /* Set the source */ 392 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_SOURCE_A, psrc); 393 394 /* Set the destination address */ 395 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_DEST_A, pdst); 396 397 /* Set the data length */ 398 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_LENGTH_A, len); 399 400 /* Set the IV */ 401 if (iv != NULL) { 402 bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, 403 SB_CBC_IV, iv, 4); 404 control |= SB_CTL_CBC; 405 } 406 407 /* Set the key */ 408 bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, SB_WKEY, key, 4); 409 410 /* Ask the security block to do it */ 411 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A, 412 control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST); 413 414 /* 415 * Now wait until it is done. 416 * 417 * We do a busy wait. Obviously the number of iterations of 418 * the loop required to perform the AES operation depends upon 419 * the number of bytes to process. 420 * 421 * On a 500 MHz Geode LX we see 422 * 423 * length (bytes) typical max iterations 424 * 16 12 425 * 64 22 426 * 256 59 427 * 1024 212 428 * 8192 1,537 429 * 430 * Since we have a maximum size of operation defined in 431 * GLXSB_MAX_AES_LEN, we use this constant to decide how long 432 * to wait. Allow an order of magnitude longer than it should 433 * really take, just in case. 434 */ 435 for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) { 436 status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A); 437 438 if ((status & SB_CTL_ST) == 0) /* Done */ 439 return; 440 } 441 442 aprint_error_dev(sc->sc_dev, "operation failed to complete\n"); 443 } 444 445 int 446 glxsb_crypto_process(void *aux, struct cryptop *crp, int hint) 447 { 448 struct glxsb_softc *sc = aux; 449 struct glxsb_session *ses; 450 struct cryptodesc *crd; 451 char *op_src, *op_dst; 452 uint32_t op_psrc, op_pdst; 453 uint8_t op_iv[SB_AES_BLOCK_SIZE], *piv; 454 int sesn, err = 0; 455 int len, tlen, xlen; 456 int offset; 457 uint32_t control; 458 int s; 459 460 s = splnet(); 461 462 if (crp == NULL || crp->crp_callback == NULL) { 463 err = EINVAL; 464 goto out; 465 } 466 crd = crp->crp_desc; 467 if (crd == NULL || crd->crd_next != NULL || 468 crd->crd_alg != CRYPTO_AES_CBC || 469 (crd->crd_len % SB_AES_BLOCK_SIZE) != 0) { 470 err = EINVAL; 471 goto out; 472 } 473 474 sesn = GLXSB_SESSION(crp->crp_sid); 475 if (sesn >= sc->sc_nsessions) { 476 err = EINVAL; 477 goto out; 478 } 479 ses = &sc->sc_sessions[sesn]; 480 481 /* How much of our buffer will we need to use? */ 482 xlen = crd->crd_len > GLXSB_MAX_AES_LEN ? 483 GLXSB_MAX_AES_LEN : crd->crd_len; 484 485 /* 486 * XXX Check if we can have input == output on Geode LX. 487 * XXX In the meantime, use two separate (adjacent) buffers. 488 */ 489 op_src = sc->sc_dma.dma_vaddr; 490 op_dst = (char *)sc->sc_dma.dma_vaddr + xlen; 491 492 op_psrc = sc->sc_dma.dma_paddr; 493 op_pdst = sc->sc_dma.dma_paddr + xlen; 494 495 if (crd->crd_flags & CRD_F_ENCRYPT) { 496 control = SB_CTL_ENC; 497 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 498 memcpy(op_iv, crd->crd_iv, sizeof(op_iv)); 499 else 500 memcpy(op_iv, ses->ses_iv, sizeof(op_iv)); 501 502 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { 503 if (crp->crp_flags & CRYPTO_F_IMBUF) 504 m_copyback((struct mbuf *)crp->crp_buf, 505 crd->crd_inject, sizeof(op_iv), op_iv); 506 else if (crp->crp_flags & CRYPTO_F_IOV) 507 cuio_copyback((struct uio *)crp->crp_buf, 508 crd->crd_inject, sizeof(op_iv), op_iv); 509 else 510 bcopy(op_iv, 511 (char *)crp->crp_buf + crd->crd_inject, 512 sizeof(op_iv)); 513 } 514 } else { 515 control = SB_CTL_DEC; 516 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 517 memcpy(op_iv, crd->crd_iv, sizeof(op_iv)); 518 else { 519 if (crp->crp_flags & CRYPTO_F_IMBUF) 520 m_copydata((struct mbuf *)crp->crp_buf, 521 crd->crd_inject, sizeof(op_iv), op_iv); 522 else if (crp->crp_flags & CRYPTO_F_IOV) 523 cuio_copydata((struct uio *)crp->crp_buf, 524 crd->crd_inject, sizeof(op_iv), op_iv); 525 else 526 bcopy((char *)crp->crp_buf + crd->crd_inject, 527 op_iv, sizeof(op_iv)); 528 } 529 } 530 531 offset = 0; 532 tlen = crd->crd_len; 533 piv = op_iv; 534 535 /* Process the data in GLXSB_MAX_AES_LEN chunks */ 536 while (tlen > 0) { 537 len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen; 538 539 if (crp->crp_flags & CRYPTO_F_IMBUF) 540 m_copydata((struct mbuf *)crp->crp_buf, 541 crd->crd_skip + offset, len, op_src); 542 else if (crp->crp_flags & CRYPTO_F_IOV) 543 cuio_copydata((struct uio *)crp->crp_buf, 544 crd->crd_skip + offset, len, op_src); 545 else 546 bcopy((char *)crp->crp_buf + crd->crd_skip + offset, 547 op_src, len); 548 549 glxsb_dma_pre_op(sc, &sc->sc_dma); 550 551 glxsb_aes(sc, control, op_psrc, op_pdst, ses->ses_key, 552 len, op_iv); 553 554 glxsb_dma_post_op(sc, &sc->sc_dma); 555 556 if (crp->crp_flags & CRYPTO_F_IMBUF) 557 m_copyback((struct mbuf *)crp->crp_buf, 558 crd->crd_skip + offset, len, op_dst); 559 else if (crp->crp_flags & CRYPTO_F_IOV) 560 cuio_copyback((struct uio *)crp->crp_buf, 561 crd->crd_skip + offset, len, op_dst); 562 else 563 memcpy((char *)crp->crp_buf + crd->crd_skip + offset, 564 op_dst, len); 565 566 offset += len; 567 tlen -= len; 568 569 if (tlen <= 0) { /* Ideally, just == 0 */ 570 /* Finished - put the IV in session IV */ 571 piv = ses->ses_iv; 572 } 573 574 /* 575 * Copy out last block for use as next iteration/session IV. 576 * 577 * piv is set to op_iv[] before the loop starts, but is 578 * set to ses->ses_iv if we're going to exit the loop this 579 * time. 580 */ 581 if (crd->crd_flags & CRD_F_ENCRYPT) { 582 memcpy(piv, op_dst + len - sizeof(op_iv), 583 sizeof(op_iv)); 584 } else { 585 /* Decryption, only need this if another iteration */ 586 if (tlen > 0) { 587 memcpy(piv, op_src + len - sizeof(op_iv), 588 sizeof(op_iv)); 589 } 590 } 591 } 592 593 /* All AES processing has now been done. */ 594 595 memset(sc->sc_dma.dma_vaddr, 0, xlen * 2); 596 out: 597 crp->crp_etype = err; 598 crypto_done(crp); 599 splx(s); 600 return (err); 601 } 602 603 int 604 glxsb_dma_alloc(struct glxsb_softc *sc, int size, struct glxsb_dma_map *dma) 605 { 606 int rc; 607 608 dma->dma_nsegs = 1; 609 dma->dma_size = size; 610 611 rc = bus_dmamap_create(sc->sc_dmat, size, dma->dma_nsegs, size, 612 0, BUS_DMA_NOWAIT, &dma->dma_map); 613 if (rc != 0) { 614 aprint_error_dev(sc->sc_dev, 615 "couldn't create DMA map for %d bytes (%d)\n", size, rc); 616 617 goto fail0; 618 } 619 620 rc = bus_dmamem_alloc(sc->sc_dmat, size, SB_AES_ALIGN, 0, 621 &dma->dma_seg, dma->dma_nsegs, &dma->dma_nsegs, BUS_DMA_NOWAIT); 622 if (rc != 0) { 623 aprint_error_dev(sc->sc_dev, 624 "couldn't allocate DMA memory of %d bytes (%d)\n", 625 size, rc); 626 627 goto fail1; 628 } 629 630 rc = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, 1, size, 631 &dma->dma_vaddr, BUS_DMA_NOWAIT); 632 if (rc != 0) { 633 aprint_error_dev(sc->sc_dev, 634 "couldn't map DMA memory for %d bytes (%d)\n", size, rc); 635 636 goto fail2; 637 } 638 639 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 640 size, NULL, BUS_DMA_NOWAIT); 641 if (rc != 0) { 642 aprint_error_dev(sc->sc_dev, 643 "couldn't load DMA memory for %d bytes (%d)\n", size, rc); 644 645 goto fail3; 646 } 647 648 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 649 650 return 0; 651 652 fail3: 653 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 654 fail2: 655 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs); 656 fail1: 657 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 658 fail0: 659 return rc; 660 } 661 662 void 663 glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 664 { 665 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size, 666 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 667 } 668 669 void 670 glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 671 { 672 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size, 673 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 674 } 675 676 void 677 glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 678 { 679 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 680 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 681 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs); 682 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 683 } 684