1 /* $NetBSD: glxsb.c,v 1.2 2007/07/09 20:52:18 ad Exp $ */ 2 /* $OpenBSD: glxsb.c,v 1.7 2007/02/12 14:31:45 tom Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org> 6 * Copyright (c) 2003, 2004 Theo de Raadt 7 * Copyright (c) 2003 Jason Wright 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for the security block on the AMD Geode LX processors 24 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/device.h> 31 #include <sys/malloc.h> 32 #include <sys/mbuf.h> 33 #include <sys/types.h> 34 #include <sys/callout.h> 35 #include <sys/rnd.h> 36 37 #include <machine/bus.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 42 #include <opencrypto/cryptodev.h> 43 #include <crypto/rijndael/rijndael.h> 44 45 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */ 46 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */ 47 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */ 48 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */ 49 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */ 50 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */ 51 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */ 52 53 /* For GLD_MSR_CTRL: */ 54 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */ 55 #define SB_GMC_DIV1 0x0001 56 #define SB_GMC_DIV2 0x0002 57 #define SB_GMC_DIV3 0x0003 58 #define SB_GMC_DIV_MASK 0x0003 59 #define SB_GMC_SBI 0x0004 /* AES swap bits */ 60 #define SB_GMC_SBY 0x0008 /* AES swap bytes */ 61 #define SB_GMC_TW 0x0010 /* Time write (EEPROM) */ 62 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */ 63 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */ 64 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */ 65 #define SB_GMC_T_SEL3 0x0300 /* RNG LFSR+whitener */ 66 #define SB_GMC_T_SEL_MASK 0x0300 67 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */ 68 #define SB_GMC_T_TM 0x0800 /* RNG test mode */ 69 /* (deterministic) */ 70 71 /* Security Block configuration/control registers (offsets from base) */ 72 73 #define SB_CTL_A 0x0000 /* RW - SB Control A */ 74 #define SB_CTL_B 0x0004 /* RW - SB Control B */ 75 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */ 76 #define SB_SOURCE_A 0x0010 /* RW - Source A */ 77 #define SB_DEST_A 0x0014 /* RW - Destination A */ 78 #define SB_LENGTH_A 0x0018 /* RW - Length A */ 79 #define SB_SOURCE_B 0x0020 /* RW - Source B */ 80 #define SB_DEST_B 0x0024 /* RW - Destination B */ 81 #define SB_LENGTH_B 0x0028 /* RW - Length B */ 82 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */ 83 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */ 84 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */ 85 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */ 86 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */ 87 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */ 88 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */ 89 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */ 90 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */ 91 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */ 92 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */ 93 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */ 94 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */ 95 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */ 96 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */ 97 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */ 98 99 /* For SB_CTL_A and _B */ 100 #define SB_CTL_ST 0x0001 /* Start operation (enc/dec) */ 101 #define SB_CTL_ENC 0x0002 /* Encrypt (0 is decrypt) */ 102 #define SB_CTL_DEC 0x0000 /* Decrypt */ 103 #define SB_CTL_WK 0x0004 /* Use writable key (we set) */ 104 #define SB_CTL_DC 0x0008 /* Destination coherent */ 105 #define SB_CTL_SC 0x0010 /* Source coherent */ 106 #define SB_CTL_CBC 0x0020 /* CBC (0 is ECB) */ 107 108 /* For SB_AES_INT */ 109 #define SB_AI_DISABLE_AES_A 0x0001 /* Disable AES A compl int */ 110 #define SB_AI_ENABLE_AES_A 0x0000 /* Enable AES A compl int */ 111 #define SB_AI_DISABLE_AES_B 0x0002 /* Disable AES B compl int */ 112 #define SB_AI_ENABLE_AES_B 0x0000 /* Enable AES B compl int */ 113 #define SB_AI_DISABLE_EEPROM 0x0004 /* Disable EEPROM op comp int */ 114 #define SB_AI_ENABLE_EEPROM 0x0000 /* Enable EEPROM op compl int */ 115 #define SB_AI_AES_A_COMPLETE 0x0100 /* AES A operation complete */ 116 #define SB_AI_AES_B_COMPLETE 0x0200 /* AES B operation complete */ 117 #define SB_AI_EEPROM_COMPLETE 0x0400 /* EEPROM operation complete */ 118 119 #define SB_RNS_TRNG_VALID 0x0001 /* in SB_RANDOM_NUM_STATUS */ 120 121 #define SB_MEM_SIZE 0x0810 /* Size of memory block */ 122 123 #define SB_AES_ALIGN 0x0010 /* Source and dest buffers */ 124 /* must be 16-byte aligned */ 125 #define SB_AES_BLOCK_SIZE 0x0010 126 127 /* 128 * The Geode LX security block AES acceleration doesn't perform scatter- 129 * gather: it just takes source and destination addresses. Therefore the 130 * plain- and ciphertexts need to be contiguous. To this end, we allocate 131 * a buffer for both, and accept the overhead of copying in and out. If 132 * the number of bytes in one operation is bigger than allowed for by the 133 * buffer (buffer is twice the size of the max length, as it has both input 134 * and output) then we have to perform multiple encryptions/decryptions. 135 */ 136 #define GLXSB_MAX_AES_LEN 16384 137 138 struct glxsb_dma_map { 139 bus_dmamap_t dma_map; 140 bus_dma_segment_t dma_seg; 141 int dma_nsegs; 142 int dma_size; 143 void * dma_vaddr; 144 uint32_t dma_paddr; 145 }; 146 struct glxsb_session { 147 uint32_t ses_key[4]; 148 uint8_t ses_iv[SB_AES_BLOCK_SIZE]; 149 int ses_klen; 150 int ses_used; 151 }; 152 153 struct glxsb_softc { 154 struct device sc_dev; 155 bus_space_tag_t sc_iot; 156 bus_space_handle_t sc_ioh; 157 struct callout sc_co; 158 159 bus_dma_tag_t sc_dmat; 160 struct glxsb_dma_map sc_dma; 161 int32_t sc_cid; 162 int sc_nsessions; 163 struct glxsb_session *sc_sessions; 164 165 rndsource_element_t sc_rnd_source; 166 }; 167 168 int glxsb_match(struct device *, struct cfdata *, void *); 169 void glxsb_attach(struct device *, struct device *, void *); 170 void glxsb_rnd(void *); 171 172 CFATTACH_DECL(glxsb, sizeof(struct glxsb_softc), glxsb_match, glxsb_attach, 173 NULL, NULL); 174 175 #define GLXSB_SESSION(sid) ((sid) & 0x0fffffff) 176 #define GLXSB_SID(crd,ses) (((crd) << 28) | ((ses) & 0x0fffffff)) 177 178 int glxsb_crypto_setup(struct glxsb_softc *); 179 int glxsb_crypto_newsession(void *, uint32_t *, struct cryptoini *); 180 int glxsb_crypto_process(void *, struct cryptop *, int); 181 int glxsb_crypto_freesession(void *, uint64_t); 182 static __inline void glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t, 183 uint32_t, void *, int, void *); 184 185 int glxsb_dma_alloc(struct glxsb_softc *, int, struct glxsb_dma_map *); 186 void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *); 187 void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *); 188 void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *); 189 190 int 191 glxsb_match(struct device *parent, struct cfdata *match, void *aux) 192 { 193 struct pci_attach_args *pa = aux; 194 195 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 196 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_GEODELX_AES) 197 return (1); 198 199 return (0); 200 } 201 202 void 203 glxsb_attach(struct device *parent, struct device *self, void *aux) 204 { 205 struct glxsb_softc *sc = (void *) self; 206 struct pci_attach_args *pa = aux; 207 bus_addr_t membase; 208 bus_size_t memsize; 209 uint64_t msr; 210 uint32_t intr; 211 212 msr = rdmsr(SB_GLD_MSR_CAP); 213 if ((msr & 0xFFFF00) != 0x130400) { 214 printf(": unknown ID 0x%x\n", (int) ((msr & 0xFFFF00) >> 16)); 215 return; 216 } 217 218 /* printf(": revision %d", (int) (msr & 0xFF)); */ 219 220 /* Map in the security block configuration/control registers */ 221 if (pci_mapreg_map(pa, PCI_MAPREG_START, 222 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 223 &sc->sc_iot, &sc->sc_ioh, &membase, &memsize)) { 224 printf(": can't find mem space\n"); 225 return; 226 } 227 228 /* 229 * Configure the Security Block. 230 * 231 * We want to enable the noise generator (T_NE), and enable the 232 * linear feedback shift register and whitener post-processing 233 * (T_SEL = 3). Also ensure that test mode (deterministic values) 234 * is disabled. 235 */ 236 msr = rdmsr(SB_GLD_MSR_CTRL); 237 msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK); 238 msr |= SB_GMC_T_NE | SB_GMC_T_SEL3; 239 #if 0 240 msr |= SB_GMC_SBI | SB_GMC_SBY; /* for AES, if necessary */ 241 #endif 242 wrmsr(SB_GLD_MSR_CTRL, msr); 243 244 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 245 RND_TYPE_RNG, RND_FLAG_NO_ESTIMATE); 246 247 /* Install a periodic collector for the "true" (AMD's word) RNG */ 248 callout_init(&sc->sc_co, 0); 249 callout_setfunc(&sc->sc_co, glxsb_rnd, sc); 250 glxsb_rnd(sc); 251 printf(": RNG"); 252 253 /* We don't have an interrupt handler, so disable completion INTs */ 254 intr = SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B | 255 SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE | 256 SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE; 257 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_AES_INT, intr); 258 259 sc->sc_dmat = pa->pa_dmat; 260 261 if (glxsb_crypto_setup(sc)) 262 printf(" AES"); 263 264 printf("\n"); 265 } 266 267 void 268 glxsb_rnd(void *v) 269 { 270 struct glxsb_softc *sc = v; 271 uint32_t status, value; 272 extern int hz; 273 274 status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM_STATUS); 275 if (status & SB_RNS_TRNG_VALID) { 276 value = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM); 277 rnd_add_uint32(&sc->sc_rnd_source, value); 278 } 279 280 callout_schedule(&sc->sc_co, (hz > 100) ? (hz / 100) : 1); 281 } 282 283 int 284 glxsb_crypto_setup(struct glxsb_softc *sc) 285 { 286 287 /* Allocate a contiguous DMA-able buffer to work in */ 288 if (glxsb_dma_alloc(sc, GLXSB_MAX_AES_LEN * 2, &sc->sc_dma) != 0) 289 return 0; 290 291 sc->sc_cid = crypto_get_driverid(0); 292 if (sc->sc_cid < 0) 293 return 0; 294 295 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 296 glxsb_crypto_newsession, glxsb_crypto_freesession, 297 glxsb_crypto_process, sc); 298 299 sc->sc_nsessions = 0; 300 301 return 1; 302 } 303 304 int 305 glxsb_crypto_newsession(void *aux, uint32_t *sidp, struct cryptoini *cri) 306 { 307 struct glxsb_softc *sc = aux; 308 struct glxsb_session *ses = NULL; 309 int sesn; 310 311 if (sc == NULL || sidp == NULL || cri == NULL || 312 cri->cri_next != NULL || cri->cri_alg != CRYPTO_AES_CBC || 313 cri->cri_klen != 128) 314 return (EINVAL); 315 316 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 317 if (sc->sc_sessions[sesn].ses_used == 0) { 318 ses = &sc->sc_sessions[sesn]; 319 break; 320 } 321 } 322 323 if (ses == NULL) { 324 sesn = sc->sc_nsessions; 325 ses = malloc((sesn + 1) * sizeof(*ses), M_DEVBUF, M_NOWAIT); 326 if (ses == NULL) 327 return (ENOMEM); 328 if (sesn != 0) { 329 bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 330 bzero(sc->sc_sessions, sesn * sizeof(*ses)); 331 free(sc->sc_sessions, M_DEVBUF); 332 } 333 sc->sc_sessions = ses; 334 ses = &sc->sc_sessions[sesn]; 335 sc->sc_nsessions++; 336 } 337 338 bzero(ses, sizeof(*ses)); 339 ses->ses_used = 1; 340 341 arc4randbytes(ses->ses_iv, sizeof(ses->ses_iv)); 342 ses->ses_klen = cri->cri_klen; 343 344 /* Copy the key (Geode LX wants the primary key only) */ 345 bcopy(cri->cri_key, ses->ses_key, sizeof(ses->ses_key)); 346 347 *sidp = GLXSB_SID(0, sesn); 348 return (0); 349 } 350 351 int 352 glxsb_crypto_freesession(void *aux, uint64_t tid) 353 { 354 struct glxsb_softc *sc = aux; 355 int sesn; 356 uint32_t sid = ((uint32_t)tid) & 0xffffffff; 357 358 if (sc == NULL) 359 return (EINVAL); 360 sesn = GLXSB_SESSION(sid); 361 if (sesn >= sc->sc_nsessions) 362 return (EINVAL); 363 bzero(&sc->sc_sessions[sesn], sizeof(sc->sc_sessions[sesn])); 364 return (0); 365 } 366 367 /* 368 * Must be called at splnet() or higher 369 */ 370 static __inline void 371 glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc, 372 uint32_t pdst, void *key, int len, void *iv) 373 { 374 uint32_t status; 375 int i; 376 377 if (len & 0xF) { 378 printf("%s: len must be a multiple of 16 (not %d)\n", 379 sc->sc_dev.dv_xname, len); 380 return; 381 } 382 383 /* Set the source */ 384 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_SOURCE_A, psrc); 385 386 /* Set the destination address */ 387 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_DEST_A, pdst); 388 389 /* Set the data length */ 390 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_LENGTH_A, len); 391 392 /* Set the IV */ 393 if (iv != NULL) { 394 bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, 395 SB_CBC_IV, iv, 4); 396 control |= SB_CTL_CBC; 397 } 398 399 /* Set the key */ 400 bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, SB_WKEY, key, 4); 401 402 /* Ask the security block to do it */ 403 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A, 404 control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST); 405 406 /* 407 * Now wait until it is done. 408 * 409 * We do a busy wait. Obviously the number of iterations of 410 * the loop required to perform the AES operation depends upon 411 * the number of bytes to process. 412 * 413 * On a 500 MHz Geode LX we see 414 * 415 * length (bytes) typical max iterations 416 * 16 12 417 * 64 22 418 * 256 59 419 * 1024 212 420 * 8192 1,537 421 * 422 * Since we have a maximum size of operation defined in 423 * GLXSB_MAX_AES_LEN, we use this constant to decide how long 424 * to wait. Allow an order of magnitude longer than it should 425 * really take, just in case. 426 */ 427 for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) { 428 status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A); 429 430 if ((status & SB_CTL_ST) == 0) /* Done */ 431 return; 432 } 433 434 printf("%s: operation failed to complete\n", sc->sc_dev.dv_xname); 435 } 436 437 int 438 glxsb_crypto_process(void *aux, struct cryptop *crp, int hint) 439 { 440 struct glxsb_softc *sc = aux; 441 struct glxsb_session *ses; 442 struct cryptodesc *crd; 443 char *op_src, *op_dst; 444 uint32_t op_psrc, op_pdst; 445 uint8_t op_iv[SB_AES_BLOCK_SIZE], *piv; 446 int sesn, err = 0; 447 int len, tlen, xlen; 448 int offset; 449 uint32_t control; 450 int s; 451 452 s = splnet(); 453 454 if (crp == NULL || crp->crp_callback == NULL) { 455 err = EINVAL; 456 goto out; 457 } 458 crd = crp->crp_desc; 459 if (crd == NULL || crd->crd_next != NULL || 460 crd->crd_alg != CRYPTO_AES_CBC || 461 (crd->crd_len % SB_AES_BLOCK_SIZE) != 0) { 462 err = EINVAL; 463 goto out; 464 } 465 466 sesn = GLXSB_SESSION(crp->crp_sid); 467 if (sesn >= sc->sc_nsessions) { 468 err = EINVAL; 469 goto out; 470 } 471 ses = &sc->sc_sessions[sesn]; 472 473 /* How much of our buffer will we need to use? */ 474 xlen = crd->crd_len > GLXSB_MAX_AES_LEN ? 475 GLXSB_MAX_AES_LEN : crd->crd_len; 476 477 /* 478 * XXX Check if we can have input == output on Geode LX. 479 * XXX In the meantime, use two separate (adjacent) buffers. 480 */ 481 op_src = sc->sc_dma.dma_vaddr; 482 op_dst = (char *)sc->sc_dma.dma_vaddr + xlen; 483 484 op_psrc = sc->sc_dma.dma_paddr; 485 op_pdst = sc->sc_dma.dma_paddr + xlen; 486 487 if (crd->crd_flags & CRD_F_ENCRYPT) { 488 control = SB_CTL_ENC; 489 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 490 bcopy(crd->crd_iv, op_iv, sizeof(op_iv)); 491 else 492 bcopy(ses->ses_iv, op_iv, sizeof(op_iv)); 493 494 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { 495 if (crp->crp_flags & CRYPTO_F_IMBUF) 496 m_copyback((struct mbuf *)crp->crp_buf, 497 crd->crd_inject, sizeof(op_iv), op_iv); 498 else if (crp->crp_flags & CRYPTO_F_IOV) 499 cuio_copyback((struct uio *)crp->crp_buf, 500 crd->crd_inject, sizeof(op_iv), op_iv); 501 else 502 bcopy(op_iv, 503 (char *)crp->crp_buf + crd->crd_inject, 504 sizeof(op_iv)); 505 } 506 } else { 507 control = SB_CTL_DEC; 508 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 509 bcopy(crd->crd_iv, op_iv, sizeof(op_iv)); 510 else { 511 if (crp->crp_flags & CRYPTO_F_IMBUF) 512 m_copydata((struct mbuf *)crp->crp_buf, 513 crd->crd_inject, sizeof(op_iv), op_iv); 514 else if (crp->crp_flags & CRYPTO_F_IOV) 515 cuio_copydata((struct uio *)crp->crp_buf, 516 crd->crd_inject, sizeof(op_iv), op_iv); 517 else 518 bcopy((char *)crp->crp_buf + crd->crd_inject, 519 op_iv, sizeof(op_iv)); 520 } 521 } 522 523 offset = 0; 524 tlen = crd->crd_len; 525 piv = op_iv; 526 527 /* Process the data in GLXSB_MAX_AES_LEN chunks */ 528 while (tlen > 0) { 529 len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen; 530 531 if (crp->crp_flags & CRYPTO_F_IMBUF) 532 m_copydata((struct mbuf *)crp->crp_buf, 533 crd->crd_skip + offset, len, op_src); 534 else if (crp->crp_flags & CRYPTO_F_IOV) 535 cuio_copydata((struct uio *)crp->crp_buf, 536 crd->crd_skip + offset, len, op_src); 537 else 538 bcopy((char *)crp->crp_buf + crd->crd_skip + offset, 539 op_src, len); 540 541 glxsb_dma_pre_op(sc, &sc->sc_dma); 542 543 glxsb_aes(sc, control, op_psrc, op_pdst, ses->ses_key, 544 len, op_iv); 545 546 glxsb_dma_post_op(sc, &sc->sc_dma); 547 548 if (crp->crp_flags & CRYPTO_F_IMBUF) 549 m_copyback((struct mbuf *)crp->crp_buf, 550 crd->crd_skip + offset, len, op_dst); 551 else if (crp->crp_flags & CRYPTO_F_IOV) 552 cuio_copyback((struct uio *)crp->crp_buf, 553 crd->crd_skip + offset, len, op_dst); 554 else 555 bcopy(op_dst, (char *)crp->crp_buf + crd->crd_skip + offset, 556 len); 557 558 offset += len; 559 tlen -= len; 560 561 if (tlen <= 0) { /* Ideally, just == 0 */ 562 /* Finished - put the IV in session IV */ 563 piv = ses->ses_iv; 564 } 565 566 /* 567 * Copy out last block for use as next iteration/session IV. 568 * 569 * piv is set to op_iv[] before the loop starts, but is 570 * set to ses->ses_iv if we're going to exit the loop this 571 * time. 572 */ 573 if (crd->crd_flags & CRD_F_ENCRYPT) { 574 bcopy(op_dst + len - sizeof(op_iv), piv, sizeof(op_iv)); 575 } else { 576 /* Decryption, only need this if another iteration */ 577 if (tlen > 0) { 578 bcopy(op_src + len - sizeof(op_iv), piv, 579 sizeof(op_iv)); 580 } 581 } 582 } 583 584 /* All AES processing has now been done. */ 585 586 bzero(sc->sc_dma.dma_vaddr, xlen * 2); 587 out: 588 crp->crp_etype = err; 589 crypto_done(crp); 590 splx(s); 591 return (err); 592 } 593 594 int 595 glxsb_dma_alloc(struct glxsb_softc *sc, int size, struct glxsb_dma_map *dma) 596 { 597 int rc; 598 599 dma->dma_nsegs = 1; 600 dma->dma_size = size; 601 602 rc = bus_dmamap_create(sc->sc_dmat, size, dma->dma_nsegs, size, 603 0, BUS_DMA_NOWAIT, &dma->dma_map); 604 if (rc != 0) { 605 printf("%s: couldn't create DMA map for %d bytes (%d)\n", 606 sc->sc_dev.dv_xname, size, rc); 607 608 goto fail0; 609 } 610 611 rc = bus_dmamem_alloc(sc->sc_dmat, size, SB_AES_ALIGN, 0, 612 &dma->dma_seg, dma->dma_nsegs, &dma->dma_nsegs, BUS_DMA_NOWAIT); 613 if (rc != 0) { 614 printf("%s: couldn't allocate DMA memory of %d bytes (%d)\n", 615 sc->sc_dev.dv_xname, size, rc); 616 617 goto fail1; 618 } 619 620 rc = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, 1, size, 621 &dma->dma_vaddr, BUS_DMA_NOWAIT); 622 if (rc != 0) { 623 printf("%s: couldn't map DMA memory for %d bytes (%d)\n", 624 sc->sc_dev.dv_xname, size, rc); 625 626 goto fail2; 627 } 628 629 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 630 size, NULL, BUS_DMA_NOWAIT); 631 if (rc != 0) { 632 printf("%s: couldn't load DMA memory for %d bytes (%d)\n", 633 sc->sc_dev.dv_xname, size, rc); 634 635 goto fail3; 636 } 637 638 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 639 640 return 0; 641 642 fail3: 643 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 644 fail2: 645 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs); 646 fail1: 647 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 648 fail0: 649 return rc; 650 } 651 652 void 653 glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 654 { 655 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size, 656 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 657 } 658 659 void 660 glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 661 { 662 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size, 663 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 664 } 665 666 void 667 glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 668 { 669 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 670 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 671 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs); 672 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 673 } 674