1 /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 36 */ 37 38 /* 39 * Bits in 386 special registers: 40 */ 41 #define CR0_PE 0x00000001 /* Protected mode Enable */ 42 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 43 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 45 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 46 #define CR0_PG 0x80000000 /* PaGing enable */ 47 48 /* 49 * Bits in 486 special registers: 50 */ 51 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 52 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 54 #define CR0_NW 0x20000000 /* Not Write-through */ 55 #define CR0_CD 0x40000000 /* Cache Disable */ 56 57 /* 58 * Cyrix 486 DLC special registers, accessable as IO ports. 59 */ 60 #define CCR0 0xc0 /* configuration control register 0 */ 61 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 62 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 63 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 64 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 65 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 66 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 67 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 68 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 69 70 #define CCR1 0xc1 /* configuration control register 1 */ 71 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 72 /* the remaining 7 bits of this register are reserved */ 73 74 /* 75 * the following four 3-byte registers control the non-cacheable regions. 76 * These registers must be written as three seperate bytes. 77 * 78 * NCRx+0: A31-A24 of starting address 79 * NCRx+1: A23-A16 of starting address 80 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 81 * 82 * The non-cacheable region's starting address must be aligned to the 83 * size indicated by the NCR_SIZE_xx field. 84 */ 85 #define NCR1 0xc4 86 #define NCR2 0xc7 87 #define NCR3 0xca 88 #define NCR4 0xcd 89 90 #define NCR_SIZE_0K 0 91 #define NCR_SIZE_4K 1 92 #define NCR_SIZE_8K 2 93 #define NCR_SIZE_16K 3 94 #define NCR_SIZE_32K 4 95 #define NCR_SIZE_64K 5 96 #define NCR_SIZE_128K 6 97 #define NCR_SIZE_256K 7 98 #define NCR_SIZE_512K 8 99 #define NCR_SIZE_1M 9 100 #define NCR_SIZE_2M 10 101 #define NCR_SIZE_4M 11 102 #define NCR_SIZE_8M 12 103 #define NCR_SIZE_16M 13 104 #define NCR_SIZE_32M 14 105 #define NCR_SIZE_4G 15 106 107