1 /* $NetBSD: specialreg.h,v 1.9 1999/12/13 01:31:30 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 36 */ 37 38 /* 39 * Bits in 386 special registers: 40 */ 41 #define CR0_PE 0x00000001 /* Protected mode Enable */ 42 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 43 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 45 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 46 #define CR0_PG 0x80000000 /* PaGing enable */ 47 48 /* 49 * Bits in 486 special registers: 50 */ 51 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 52 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 54 #define CR0_NW 0x20000000 /* Not Write-through */ 55 #define CR0_CD 0x40000000 /* Cache Disable */ 56 57 /* 58 * Cyrix 486 DLC special registers, accessable as IO ports. 59 */ 60 #define CCR0 0xc0 /* configuration control register 0 */ 61 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 62 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 63 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 64 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 65 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 66 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 67 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 68 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 69 70 #define CCR1 0xc1 /* configuration control register 1 */ 71 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 72 /* the remaining 7 bits of this register are reserved */ 73 74 /* 75 * bits in the pentiums %cr4 register: 76 */ 77 78 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 79 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 80 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 81 #define CR4_DE 0x00000008 /* debugging extension */ 82 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 83 #define CR4_PAE 0x00000020 /* physical address extension enable */ 84 #define CR4_MCE 0x00000040 /* machine check enable */ 85 #define CR4_PGE 0x00000080 /* page global enable */ 86 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 87 88 /* 89 * CPUID "features" bits: 90 */ 91 92 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 93 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 94 #define CPUID_DE 0x00000004 /* has debugging extension */ 95 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 96 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 97 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 98 #define CPUID_PAE 0x00000040 /* has phys address extension */ 99 #define CPUID_MCE 0x00000080 /* has machine check exception */ 100 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 101 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 102 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 103 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 104 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 105 #define CPUID_PGE 0x00002000 /* has page global extension */ 106 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 107 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 108 #define CPUID_FGPAT 0x00010000 /* Page Attribute Table */ 109 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 110 #define CPUID_PN 0x00040000 /* processor serial number */ 111 #define CPUID_B19 0x00080000 /* reserved */ 112 #define CPUID_B20 0x00100000 /* reserved */ 113 #define CPUID_B21 0x00200000 /* reserved */ 114 #define CPUID_B22 0x00400000 /* reserved */ 115 #define CPUID_MMX 0x00800000 /* MMX supported */ 116 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 117 #define CPUID_XMM 0x02000000 /* streaming SIMD extensions */ 118 /* bits 26->31 also reserved. */ 119 120 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR" 121 #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21FGPAT\22PSE36\23PN\24B19\25B20\26B21\27B22\30MMX\31FXSR\32XMM\33B26\34B27\35B28\36B29\37B30\40B31" 122 123 124 /* 125 * the following four 3-byte registers control the non-cacheable regions. 126 * These registers must be written as three seperate bytes. 127 * 128 * NCRx+0: A31-A24 of starting address 129 * NCRx+1: A23-A16 of starting address 130 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 131 * 132 * The non-cacheable region's starting address must be aligned to the 133 * size indicated by the NCR_SIZE_xx field. 134 */ 135 #define NCR1 0xc4 136 #define NCR2 0xc7 137 #define NCR3 0xca 138 #define NCR4 0xcd 139 140 #define NCR_SIZE_0K 0 141 #define NCR_SIZE_4K 1 142 #define NCR_SIZE_8K 2 143 #define NCR_SIZE_16K 3 144 #define NCR_SIZE_32K 4 145 #define NCR_SIZE_64K 5 146 #define NCR_SIZE_128K 6 147 #define NCR_SIZE_256K 7 148 #define NCR_SIZE_512K 8 149 #define NCR_SIZE_1M 9 150 #define NCR_SIZE_2M 10 151 #define NCR_SIZE_4M 11 152 #define NCR_SIZE_8M 12 153 #define NCR_SIZE_16M 13 154 #define NCR_SIZE_32M 14 155 #define NCR_SIZE_4G 15 156 157