1 /* $NetBSD: pmap.h,v 1.126 2020/07/19 13:55:09 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Charles D. Cranor and Washington University. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Copyright (c) 2001 Wasabi Systems, Inc. 30 * All rights reserved. 31 * 32 * Written by Frank van der Linden for Wasabi Systems, Inc. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed for the NetBSD Project by 45 * Wasabi Systems, Inc. 46 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 47 * or promote products derived from this software without specific prior 48 * written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 #ifndef _I386_PMAP_H_ 64 #define _I386_PMAP_H_ 65 66 #if defined(_KERNEL_OPT) 67 #include "opt_xen.h" 68 #endif 69 70 #include <sys/atomic.h> 71 72 #include <i386/pte.h> 73 #include <machine/segments.h> 74 #if defined(_KERNEL) 75 #include <machine/cpufunc.h> 76 #endif 77 78 #include <uvm/uvm_object.h> 79 #ifdef XENPV 80 #include <xen/xenfunc.h> 81 #include <xen/xenpmap.h> 82 #endif /* XENPV */ 83 84 /* 85 * see pte.h for a description of i386 MMU terminology and hardware 86 * interface. 87 * 88 * a pmap describes a processes' 4GB virtual address space. when PAE 89 * is not in use, this virtual address space can be broken up into 1024 4MB 90 * regions which are described by PDEs in the PDP. the PDEs are defined as 91 * follows: 92 * 93 * (ranges are inclusive -> exclusive, just like vm_map_entry start/end) 94 * (the following assumes that KERNBASE is 0xc0000000) 95 * 96 * PDE#s VA range usage 97 * 0->766 0x0 -> 0xbfc00000 user address space 98 * 767 0xbfc00000-> recursive mapping of PDP (used for 99 * 0xc0000000 linear mapping of PTPs) 100 * 768->1023 0xc0000000-> kernel address space (constant 101 * 0xffc00000 across all pmap's/processes) 102 * <end> 103 * 104 * 105 * note: a recursive PDP mapping provides a way to map all the PTEs for 106 * a 4GB address space into a linear chunk of virtual memory. in other 107 * words, the PTE for page 0 is the first int mapped into the 4MB recursive 108 * area. the PTE for page 1 is the second int. the very last int in the 109 * 4MB range is the PTE that maps VA 0xfffff000 (the last page in a 4GB 110 * address). 111 * 112 * all pmap's PD's must have the same values in slots 768->1023 so that 113 * the kernel is always mapped in every process. these values are loaded 114 * into the PD at pmap creation time. 115 * 116 * at any one time only one pmap can be active on a processor. this is 117 * the pmap whose PDP is pointed to by processor register %cr3. this pmap 118 * will have all its PTEs mapped into memory at the recursive mapping 119 * point (slot #767 as show above). when the pmap code wants to find the 120 * PTE for a virtual address, all it has to do is the following: 121 * 122 * address of PTE = (767 * 4MB) + (VA / PAGE_SIZE) * sizeof(pt_entry_t) 123 * = 0xbfc00000 + (VA / 4096) * 4 124 * 125 * what happens if the pmap layer is asked to perform an operation 126 * on a pmap that is not the one which is currently active? in that 127 * case we temporarily load this pmap, perform the operation, and mark 128 * the currently active one as pending lazy reload. 129 * 130 * the following figure shows the effects of the recursive PDP mapping: 131 * 132 * PDP (%cr3) 133 * +----+ 134 * | 0| -> PTP#0 that maps VA 0x0 -> 0x400000 135 * | | 136 * | | 137 * | 767| -> points back to PDP (%cr3) mapping VA 0xbfc00000 -> 0xc0000000 138 * | 768| -> first kernel PTP (maps 0xc0000000 -> 0xc0400000) 139 * | | 140 * +----+ 141 * 142 * note that the PDE#767 VA (0xbfc00000) is defined as "PTE_BASE" 143 * 144 * starting at VA 0xbfc00000 the current active PDP (%cr3) acts as a 145 * PTP: 146 * 147 * PTP#767 == PDP(%cr3) => maps VA 0xbfc00000 -> 0xc0000000 148 * +----+ 149 * | 0| -> maps the contents of PTP#0 at VA 0xbfc00000->0xbfc01000 150 * | | 151 * | | 152 * | 767| -> maps contents of PTP#767 (the PDP) at VA 0xbfeff000 153 * | 768| -> maps contents of first kernel PTP 154 * | | 155 * |1023| 156 * +----+ 157 * 158 * note that mapping of the PDP at PTP#767's VA (0xbfeff000) is 159 * defined as "PDP_BASE".... within that mapping there are two 160 * defines: 161 * "PDP_PDE" (0xbfeffbfc) is the VA of the PDE in the PDP 162 * which points back to itself. 163 * 164 * - PAE support - 165 * --------------- 166 * 167 * PAE adds another layer of indirection during address translation, breaking 168 * up the translation process in 3 different levels: 169 * - L3 page directory, containing 4 * 64-bits addresses (index determined by 170 * bits [31:30] from the virtual address). This breaks up the address space 171 * in 4 1GB regions. 172 * - the PD (L2), containing 512 64-bits addresses, breaking each L3 region 173 * in 512 * 2MB regions. 174 * - the PT (L1), also containing 512 64-bits addresses (at L1, the size of 175 * the pages is still 4K). 176 * 177 * The kernel virtual space is mapped by the last entry in the L3 page, 178 * the first 3 entries mapping the user VA space. 179 * 180 * Because the L3 has only 4 entries of 1GB each, we can't use recursive 181 * mappings at this level for PDP_PDE (this would eat up 2 of the 4GB 182 * virtual space). There are also restrictions imposed by Xen on the 183 * last entry of the L3 PD (reference count to this page cannot be 184 * bigger than 1), which makes it hard to use one L3 page per pmap to 185 * switch between pmaps using %cr3. 186 * 187 * As such, each CPU gets its own L3 page that is always loaded into its %cr3 188 * (ci_pae_l3_pd in the associated cpu_info struct). We claim that the VM has 189 * only a 2-level PTP (similar to the non-PAE case). L2 PD is now 4 contiguous 190 * pages long (corresponding to the 4 entries of the L3), and the different 191 * index/slots (like PDP_PDE) are adapted accordingly. 192 * 193 * Kernel space remains in L3[3], L3[0-2] maps the user VA space. Switching 194 * between pmaps consists in modifying the first 3 entries of the CPU's L3 page. 195 * 196 * PTE_BASE will need 4 entries in the L2 PD pages to map the L2 pages 197 * recursively. 198 * 199 * In addition, for Xen, we can't recursively map L3[3] (Xen wants the ref 200 * count on this page to be exactly one), so we use a shadow PD page for 201 * the last L2 PD. The shadow page could be static too, but to make pm_pdir[] 202 * contiguous we'll allocate/copy one page per pmap. 203 */ 204 205 /* 206 * Mask to get rid of the sign-extended part of addresses. 207 */ 208 #define VA_SIGN_MASK 0 209 #define VA_SIGN_NEG(va) ((va) | VA_SIGN_MASK) 210 /* 211 * XXXfvdl this one's not right. 212 */ 213 #define VA_SIGN_POS(va) ((va) & ~VA_SIGN_MASK) 214 215 /* 216 * the following defines identify the slots used as described above. 217 */ 218 #ifdef PAE 219 #define L2_SLOT_PTE (KERNBASE/NBPD_L2-4) /* 1532: for recursive PDP map */ 220 #define L2_SLOT_KERN (KERNBASE/NBPD_L2) /* 1536: start of kernel space */ 221 #else /* PAE */ 222 #define L2_SLOT_PTE (KERNBASE/NBPD_L2-1) /* 767: for recursive PDP map */ 223 #define L2_SLOT_KERN (KERNBASE/NBPD_L2) /* 768: start of kernel space */ 224 #endif /* PAE */ 225 226 #define L2_SLOT_KERNBASE L2_SLOT_KERN 227 228 #define PDIR_SLOT_KERN L2_SLOT_KERN 229 #define PDIR_SLOT_PTE L2_SLOT_PTE 230 231 /* 232 * the following defines give the virtual addresses of various MMU 233 * data structures: 234 * PTE_BASE: the base VA of the linear PTE mappings 235 * PDP_BASE: the base VA of the recursive mapping of the PDP 236 * PDP_PDE: the VA of the PDE that points back to the PDP 237 */ 238 239 #define PTE_BASE ((pt_entry_t *) (PDIR_SLOT_PTE * NBPD_L2)) 240 241 #define L1_BASE PTE_BASE 242 243 #define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L2_SLOT_PTE * NBPD_L1)) 244 245 #define PDP_PDE (L2_BASE + PDIR_SLOT_PTE) 246 247 #define PDP_BASE L2_BASE 248 249 /* largest value (-1 for APTP space) */ 250 #define NKL2_MAX_ENTRIES (NTOPLEVEL_PDES - (KERNBASE/NBPD_L2) - 1) 251 #define NKL1_MAX_ENTRIES (unsigned long)(NKL2_MAX_ENTRIES * NPDPG) 252 253 #define NKL2_KIMG_ENTRIES 0 /* XXX unused */ 254 255 #define NKL2_START_ENTRIES 0 /* XXX computed on runtime */ 256 #define NKL1_START_ENTRIES 0 /* XXX unused */ 257 258 #ifndef XENPV 259 #define NTOPLEVEL_PDES (PAGE_SIZE * PDP_SIZE / (sizeof (pd_entry_t))) 260 #else /* !XENPV */ 261 #ifdef PAE 262 #define NTOPLEVEL_PDES 1964 /* 1964-2047 reserved by Xen */ 263 #else /* PAE */ 264 #define NTOPLEVEL_PDES 1008 /* 1008-1023 reserved by Xen */ 265 #endif /* PAE */ 266 #endif /* !XENPV */ 267 #define NPDPG (PAGE_SIZE / sizeof (pd_entry_t)) 268 269 #define PTP_MASK_INITIALIZER { L1_MASK, L2_MASK } 270 #define PTP_FRAME_INITIALIZER { L1_FRAME, L2_FRAME } 271 #define PTP_SHIFT_INITIALIZER { L1_SHIFT, L2_SHIFT } 272 #define NKPTP_INITIALIZER { NKL1_START_ENTRIES, NKL2_START_ENTRIES } 273 #define NKPTPMAX_INITIALIZER { NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES } 274 #define NBPD_INITIALIZER { NBPD_L1, NBPD_L2 } 275 #define PDES_INITIALIZER { L2_BASE } 276 277 #define PTP_LEVELS 2 278 279 /* 280 * PTE_AVL usage: we make use of the ignored bits of the PTE 281 */ 282 #define PTE_WIRED PTE_AVL1 /* Wired Mapping */ 283 #define PTE_PVLIST PTE_AVL2 /* Mapping has entry on pvlist */ 284 #define PTE_X PTE_AVL3 /* Executable */ 285 286 /* XXX To be deleted. */ 287 #define PG_W PTE_WIRED 288 #define PG_PVLIST PTE_PVLIST 289 #define PG_X PTE_X 290 291 #include <x86/pmap.h> 292 293 #ifndef XENPV 294 #define pmap_pa2pte(a) (a) 295 #define pmap_pte2pa(a) ((a) & PTE_FRAME) 296 #define pmap_pte_set(p, n) do { *(p) = (n); } while (0) 297 #define pmap_pte_flush() /* nothing */ 298 299 #ifdef PAE 300 #define pmap_pte_cas(p, o, n) atomic_cas_64((p), (o), (n)) 301 #define pmap_pte_testset(p, n) \ 302 atomic_swap_64((volatile uint64_t *)p, n) 303 #define pmap_pte_setbits(p, b) \ 304 atomic_or_64((volatile uint64_t *)p, b) 305 #define pmap_pte_clearbits(p, b) \ 306 atomic_and_64((volatile uint64_t *)p, ~(b)) 307 #else /* PAE */ 308 #define pmap_pte_cas(p, o, n) atomic_cas_32((p), (o), (n)) 309 #define pmap_pte_testset(p, n) \ 310 atomic_swap_ulong((volatile unsigned long *)p, n) 311 #define pmap_pte_setbits(p, b) \ 312 atomic_or_ulong((volatile unsigned long *)p, b) 313 #define pmap_pte_clearbits(p, b) \ 314 atomic_and_ulong((volatile unsigned long *)p, ~(b)) 315 #endif /* PAE */ 316 317 #else /* XENPV */ 318 extern kmutex_t pte_lock; 319 320 static __inline pt_entry_t 321 pmap_pa2pte(paddr_t pa) 322 { 323 return (pt_entry_t)xpmap_ptom_masked(pa); 324 } 325 326 static __inline paddr_t 327 pmap_pte2pa(pt_entry_t pte) 328 { 329 return xpmap_mtop_masked(pte & PTE_FRAME); 330 } 331 static __inline void 332 pmap_pte_set(pt_entry_t *pte, pt_entry_t npte) 333 { 334 int s = splvm(); 335 xpq_queue_pte_update(xpmap_ptetomach(pte), npte); 336 splx(s); 337 } 338 339 static __inline pt_entry_t 340 pmap_pte_cas(volatile pt_entry_t *ptep, pt_entry_t o, pt_entry_t n) 341 { 342 pt_entry_t opte; 343 344 mutex_enter(&pte_lock); 345 opte = *ptep; 346 if (opte == o) { 347 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(ptep)), n); 348 xpq_flush_queue(); 349 } 350 mutex_exit(&pte_lock); 351 return opte; 352 } 353 354 static __inline pt_entry_t 355 pmap_pte_testset(volatile pt_entry_t *pte, pt_entry_t npte) 356 { 357 pt_entry_t opte; 358 359 mutex_enter(&pte_lock); 360 opte = *pte; 361 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), 362 npte); 363 xpq_flush_queue(); 364 mutex_exit(&pte_lock); 365 return opte; 366 } 367 368 static __inline void 369 pmap_pte_setbits(volatile pt_entry_t *pte, pt_entry_t bits) 370 { 371 mutex_enter(&pte_lock); 372 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), (*pte) | bits); 373 xpq_flush_queue(); 374 mutex_exit(&pte_lock); 375 } 376 377 static __inline void 378 pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits) 379 { 380 mutex_enter(&pte_lock); 381 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), 382 (*pte) & ~bits); 383 xpq_flush_queue(); 384 mutex_exit(&pte_lock); 385 } 386 387 static __inline void 388 pmap_pte_flush(void) 389 { 390 int s = splvm(); 391 xpq_flush_queue(); 392 splx(s); 393 } 394 395 #endif 396 397 struct vm_map; 398 struct trapframe; 399 struct pcb; 400 401 int pmap_exec_fixup(struct vm_map *, struct trapframe *, struct pcb *); 402 403 #include <x86/pmap_pv.h> 404 405 #define __HAVE_VM_PAGE_MD 406 #define VM_MDPAGE_INIT(pg) \ 407 memset(&(pg)->mdpage, 0, sizeof((pg)->mdpage)); \ 408 PMAP_PAGE_INIT(&(pg)->mdpage.mp_pp) 409 410 struct vm_page_md { 411 struct pmap_page mp_pp; 412 }; 413 414 #endif /* _I386_PMAP_H_ */ 415