1 /* $NetBSD: cpufunc.h,v 1.33 2006/08/26 20:08:07 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _I386_CPUFUNC_H_ 40 #define _I386_CPUFUNC_H_ 41 42 /* 43 * Functions to provide access to i386-specific instructions. 44 */ 45 46 #include <sys/cdefs.h> 47 #include <sys/types.h> 48 49 #include <machine/segments.h> 50 #include <machine/specialreg.h> 51 52 static __inline void 53 x86_pause(void) 54 { 55 __asm volatile("pause"); 56 } 57 58 /* 59 * XXX it's better to use real lfence insn if available. 60 * 61 * memory clobber to avoid compiler reordering. 62 */ 63 static __inline void 64 x86_lfence(void) 65 { 66 67 __asm volatile("lock; addl $0, 0(%%esp)" : : : "memory"); 68 } 69 70 static __inline void 71 x86_sfence(void) 72 { 73 74 __asm volatile("lock; addl $0, 0(%%esp)" : : : "memory"); 75 } 76 77 static __inline void 78 x86_mfence(void) 79 { 80 81 __asm volatile("lock; addl $0, 0(%%esp)" : : : "memory"); 82 } 83 84 #ifdef _KERNEL 85 86 extern unsigned int cpu_feature; 87 88 static __inline void 89 invlpg(u_int addr) 90 { 91 __asm volatile("invlpg (%0)" : : "r" (addr) : "memory"); 92 } 93 94 static __inline void 95 lidt(struct region_descriptor *region) 96 { 97 __asm volatile("lidt %0" : : "m" (*region)); 98 } 99 100 static __inline void 101 lldt(u_short sel) 102 { 103 __asm volatile("lldt %0" : : "r" (sel)); 104 } 105 106 static __inline void 107 ltr(u_short sel) 108 { 109 __asm volatile("ltr %0" : : "r" (sel)); 110 } 111 112 static __inline void 113 lcr0(u_int val) 114 { 115 __asm volatile("movl %0,%%cr0" : : "r" (val)); 116 } 117 118 static __inline u_int 119 rcr0(void) 120 { 121 u_int val; 122 __asm volatile("movl %%cr0,%0" : "=r" (val)); 123 return val; 124 } 125 126 static __inline u_int 127 rcr2(void) 128 { 129 u_int val; 130 __asm volatile("movl %%cr2,%0" : "=r" (val)); 131 return val; 132 } 133 134 static __inline void 135 lcr3(u_int val) 136 { 137 __asm volatile("movl %0,%%cr3" : : "r" (val)); 138 } 139 140 static __inline u_int 141 rcr3(void) 142 { 143 u_int val; 144 __asm volatile("movl %%cr3,%0" : "=r" (val)); 145 return val; 146 } 147 148 static __inline void 149 lcr4(u_int val) 150 { 151 __asm volatile("movl %0,%%cr4" : : "r" (val)); 152 } 153 154 static __inline u_int 155 rcr4(void) 156 { 157 u_int val; 158 __asm volatile("movl %%cr4,%0" : "=r" (val)); 159 return val; 160 } 161 162 static __inline void 163 tlbflush(void) 164 { 165 u_int val; 166 val = rcr3(); 167 lcr3(val); 168 } 169 170 static __inline void 171 tlbflushg(void) 172 { 173 /* 174 * Big hammer: flush all TLB entries, including ones from PTE's 175 * with the G bit set. This should only be necessary if TLB 176 * shootdown falls far behind. 177 * 178 * Intel Architecture Software Developer's Manual, Volume 3, 179 * System Programming, section 9.10, "Invalidating the 180 * Translation Lookaside Buffers (TLBS)": 181 * "The following operations invalidate all TLB entries, irrespective 182 * of the setting of the G flag: 183 * ... 184 * "(P6 family processors only): Writing to control register CR4 to 185 * modify the PSE, PGE, or PAE flag." 186 * 187 * (the alternatives not quoted above are not an option here.) 188 * 189 * If PGE is not in use, we reload CR3 for the benefit of 190 * pre-P6-family processors. 191 */ 192 193 #if defined(I686_CPU) 194 if (cpu_feature & CPUID_PGE) { 195 u_int cr4 = rcr4(); 196 lcr4(cr4 & ~CR4_PGE); 197 lcr4(cr4); 198 } else 199 #endif 200 tlbflush(); 201 } 202 203 204 #ifdef notyet 205 void setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl); 206 #endif 207 208 /* debug register */ 209 void dr0(caddr_t, uint32_t, uint32_t, uint32_t); 210 211 static __inline u_int 212 rdr6(void) 213 { 214 u_int val; 215 216 __asm volatile("movl %%dr6,%0" : "=r" (val)); 217 return val; 218 } 219 220 static __inline void 221 ldr6(u_int val) 222 { 223 224 __asm volatile("movl %0,%%dr6" : : "r" (val)); 225 } 226 227 /* XXXX ought to be in psl.h with spl() functions */ 228 229 static __inline void 230 disable_intr(void) 231 { 232 __asm volatile("cli"); 233 } 234 235 static __inline void 236 enable_intr(void) 237 { 238 __asm volatile("sti"); 239 } 240 241 static __inline u_long 242 read_eflags(void) 243 { 244 u_long ef; 245 246 __asm volatile("pushfl; popl %0" : "=r" (ef)); 247 return (ef); 248 } 249 250 static __inline void 251 write_eflags(u_long ef) 252 { 253 __asm volatile("pushl %0; popfl" : : "r" (ef)); 254 } 255 256 static __inline uint64_t 257 rdmsr(u_int msr) 258 { 259 uint64_t rv; 260 261 __asm volatile("rdmsr" : "=A" (rv) : "c" (msr)); 262 return (rv); 263 } 264 265 static __inline void 266 wrmsr(u_int msr, uint64_t newval) 267 { 268 __asm volatile("wrmsr" : : "A" (newval), "c" (msr)); 269 } 270 271 static __inline void 272 wbinvd(void) 273 { 274 __asm volatile("wbinvd"); 275 } 276 277 static __inline uint64_t 278 rdtsc(void) 279 { 280 uint64_t rv; 281 282 __asm volatile("rdtsc" : "=A" (rv)); 283 return (rv); 284 } 285 286 static __inline uint64_t 287 rdpmc(u_int pmc) 288 { 289 uint64_t rv; 290 291 __asm volatile("rdpmc" : "=A" (rv) : "c" (pmc)); 292 return (rv); 293 } 294 295 /* Break into DDB/KGDB. */ 296 static __inline void 297 breakpoint(void) 298 { 299 __asm volatile("int $3"); 300 } 301 302 #define read_psl() read_eflags() 303 #define write_psl(x) write_eflags(x) 304 305 /* 306 * XXX Maybe these don't belong here... 307 */ 308 309 extern int (*copyout_func)(const void *, void *, size_t); 310 extern int (*copyin_func)(const void *, void *, size_t); 311 312 int i386_copyout(const void *, void *, size_t); 313 int i486_copyout(const void *, void *, size_t); 314 315 int i386_copyin(const void *, void *, size_t); 316 317 #endif /* _KERNEL */ 318 319 #endif /* !_I386_CPUFUNC_H_ */ 320