1 /* $NetBSD: cpufunc.h,v 1.31 2005/12/28 19:09:29 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _I386_CPUFUNC_H_ 40 #define _I386_CPUFUNC_H_ 41 42 /* 43 * Functions to provide access to i386-specific instructions. 44 */ 45 46 #include <sys/cdefs.h> 47 #include <sys/types.h> 48 49 #include <machine/specialreg.h> 50 51 static __inline void 52 x86_pause(void) 53 { 54 __asm volatile("pause"); 55 } 56 57 static __inline void 58 x86_lfence(void) 59 { 60 61 /* 62 * XXX it's better to use real lfence insn if available. 63 */ 64 __asm volatile("lock; addl $0, 0(%%esp)" : : : "memory"); 65 } 66 67 #ifdef _KERNEL 68 69 extern unsigned int cpu_feature; 70 71 static __inline void 72 invlpg(u_int addr) 73 { 74 __asm volatile("invlpg (%0)" : : "r" (addr) : "memory"); 75 } 76 77 static __inline void 78 lidt(void *p) 79 { 80 __asm volatile("lidt (%0)" : : "r" (p)); 81 } 82 83 static __inline void 84 lldt(u_short sel) 85 { 86 __asm volatile("lldt %0" : : "r" (sel)); 87 } 88 89 static __inline void 90 ltr(u_short sel) 91 { 92 __asm volatile("ltr %0" : : "r" (sel)); 93 } 94 95 static __inline void 96 lcr0(u_int val) 97 { 98 __asm volatile("movl %0,%%cr0" : : "r" (val)); 99 } 100 101 static __inline u_int 102 rcr0(void) 103 { 104 u_int val; 105 __asm volatile("movl %%cr0,%0" : "=r" (val)); 106 return val; 107 } 108 109 static __inline u_int 110 rcr2(void) 111 { 112 u_int val; 113 __asm volatile("movl %%cr2,%0" : "=r" (val)); 114 return val; 115 } 116 117 static __inline void 118 lcr3(u_int val) 119 { 120 __asm volatile("movl %0,%%cr3" : : "r" (val)); 121 } 122 123 static __inline u_int 124 rcr3(void) 125 { 126 u_int val; 127 __asm volatile("movl %%cr3,%0" : "=r" (val)); 128 return val; 129 } 130 131 static __inline void 132 lcr4(u_int val) 133 { 134 __asm volatile("movl %0,%%cr4" : : "r" (val)); 135 } 136 137 static __inline u_int 138 rcr4(void) 139 { 140 u_int val; 141 __asm volatile("movl %%cr4,%0" : "=r" (val)); 142 return val; 143 } 144 145 static __inline void 146 tlbflush(void) 147 { 148 u_int val; 149 val = rcr3(); 150 lcr3(val); 151 } 152 153 static __inline void 154 tlbflushg(void) 155 { 156 /* 157 * Big hammer: flush all TLB entries, including ones from PTE's 158 * with the G bit set. This should only be necessary if TLB 159 * shootdown falls far behind. 160 * 161 * Intel Architecture Software Developer's Manual, Volume 3, 162 * System Programming, section 9.10, "Invalidating the 163 * Translation Lookaside Buffers (TLBS)": 164 * "The following operations invalidate all TLB entries, irrespective 165 * of the setting of the G flag: 166 * ... 167 * "(P6 family processors only): Writing to control register CR4 to 168 * modify the PSE, PGE, or PAE flag." 169 * 170 * (the alternatives not quoted above are not an option here.) 171 * 172 * If PGE is not in use, we reload CR3 for the benefit of 173 * pre-P6-family processors. 174 */ 175 176 #if defined(I686_CPU) 177 if (cpu_feature & CPUID_PGE) { 178 u_int cr4 = rcr4(); 179 lcr4(cr4 & ~CR4_PGE); 180 lcr4(cr4); 181 } else 182 #endif 183 tlbflush(); 184 } 185 186 187 #ifdef notyet 188 void setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl); 189 #endif 190 191 /* debug register */ 192 void dr0(caddr_t, uint32_t, uint32_t, uint32_t); 193 194 static __inline u_int 195 rdr6(void) 196 { 197 u_int val; 198 199 __asm volatile("movl %%dr6,%0" : "=r" (val)); 200 return val; 201 } 202 203 static __inline void 204 ldr6(u_int val) 205 { 206 207 __asm volatile("movl %0,%%dr6" : : "r" (val)); 208 } 209 210 /* XXXX ought to be in psl.h with spl() functions */ 211 212 static __inline void 213 disable_intr(void) 214 { 215 __asm volatile("cli"); 216 } 217 218 static __inline void 219 enable_intr(void) 220 { 221 __asm volatile("sti"); 222 } 223 224 static __inline u_long 225 read_eflags(void) 226 { 227 u_long ef; 228 229 __asm volatile("pushfl; popl %0" : "=r" (ef)); 230 return (ef); 231 } 232 233 static __inline void 234 write_eflags(u_long ef) 235 { 236 __asm volatile("pushl %0; popfl" : : "r" (ef)); 237 } 238 239 static __inline uint64_t 240 rdmsr(u_int msr) 241 { 242 uint64_t rv; 243 244 __asm volatile("rdmsr" : "=A" (rv) : "c" (msr)); 245 return (rv); 246 } 247 248 static __inline void 249 wrmsr(u_int msr, uint64_t newval) 250 { 251 __asm volatile("wrmsr" : : "A" (newval), "c" (msr)); 252 } 253 254 static __inline void 255 wbinvd(void) 256 { 257 __asm volatile("wbinvd"); 258 } 259 260 static __inline uint64_t 261 rdtsc(void) 262 { 263 uint64_t rv; 264 265 __asm volatile("rdtsc" : "=A" (rv)); 266 return (rv); 267 } 268 269 static __inline uint64_t 270 rdpmc(u_int pmc) 271 { 272 uint64_t rv; 273 274 __asm volatile("rdpmc" : "=A" (rv) : "c" (pmc)); 275 return (rv); 276 } 277 278 /* Break into DDB/KGDB. */ 279 static __inline void 280 breakpoint(void) 281 { 282 __asm volatile("int $3"); 283 } 284 285 #define read_psl() read_eflags() 286 #define write_psl(x) write_eflags(x) 287 288 /* 289 * XXX Maybe these don't belong here... 290 */ 291 292 extern int (*copyout_func)(const void *, void *, size_t); 293 extern int (*copyin_func)(const void *, void *, size_t); 294 295 int i386_copyout(const void *, void *, size_t); 296 int i486_copyout(const void *, void *, size_t); 297 298 int i386_copyin(const void *, void *, size_t); 299 300 #endif /* _KERNEL */ 301 302 #endif /* !_I386_CPUFUNC_H_ */ 303