1 /* $NetBSD: reg.h,v 1.6 2008/01/10 21:08:41 skrll Exp $ */ 2 3 /* $OpenBSD: reg.h,v 1.7 2000/06/15 17:00:37 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1998 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Michael Shalayeff. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * Copyright (c) 1990,1994 The University of Utah and 36 * the Computer Systems Laboratory at the University of Utah (CSL). 37 * All rights reserved. 38 * 39 * Permission to use, copy, modify and distribute this software is hereby 40 * granted provided that (1) source code retains these copyright, permission, 41 * and disclaimer notices, and (2) redistributions including binaries 42 * reproduce the notices in supporting documentation, and (3) all advertising 43 * materials mentioning features or use of this software display the following 44 * acknowledgement: ``This product includes software developed by the 45 * Computer Systems Laboratory at the University of Utah.'' 46 * 47 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 48 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 49 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 50 * 51 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 52 * improvements that they make and grant CSL redistribution rights. 53 * 54 * Utah $Hdr: regs.h 1.6 94/12/14$ 55 * Author: Bob Wheeler, University of Utah CSL 56 */ 57 58 #ifndef _HPPA_REG_H_ 59 #define _HPPA_REG_H_ 60 61 /* 62 * constants for registers for use with the following routines: 63 * 64 * void mtctl(reg, value) - move to control register 65 * int mfctl(reg) - move from control register 66 * int mtsp(sreg, value) - move to space register 67 * int mfsr(sreg) - move from space register 68 */ 69 70 #define CR_RCTR 0 71 #define CR_PIDR1 8 72 #define CR_PIDR2 9 73 #define CR_CCR 10 74 #define CR_SAR 11 75 #define CR_PIDR3 12 76 #define CR_PIDR4 13 77 #define CR_IVA 14 78 #define CR_EIEM 15 79 #define CR_ITMR 16 80 #define CR_PCSQ 17 81 #define CR_PCOQ 18 82 #define CR_IIR 19 83 #define CR_ISR 20 84 #define CR_IOR 21 85 #define CR_IPSW 22 86 #define CR_EIRR 23 87 #define CR_HPTMASK 24 88 #define CR_VTOP 25 89 #define CR_TR2 26 90 #define CR_TR3 27 91 #define CR_HVTP 28 /* points to a faulted HVT slot on LC cpus */ 92 #define CR_TR5 29 93 #define CR_UPADDR 30 /* paddr of U-area of curproc */ 94 #define CR_TR7 31 95 96 /* 97 * Diagnostic registers and bit positions 98 */ 99 #define DR_CPUCFG 0 100 101 #define DR0_PCXS_DHPMC 10 /* r/c D-cache error flag */ 102 #define DR0_PCXS_ILPMC 14 /* r/c I-cache error flag */ 103 #define DR0_PCXS_EQWSTO 16 /* r/w enable quad-word stores */ 104 #define DR0_PCXS_IHE 18 /* r/w I-cache sid hash enable */ 105 #define DR0_PCXS_DOMAIN 19 106 #define DR0_PCXS_DHE 20 /* r/w D-cache sid hash enable */ 107 108 #define DR0_PCXT_DHPMC 10 /* r/c L1 D-cache error flag */ 109 #define DR0_PCXT_ILPMC 14 /* r/c L1 I-cache error flag */ 110 #define DR0_PCXT_IHE 18 /* r/w I-cache sid hash enable */ 111 #define DR0_PCXT_DHE 20 /* r/w D-cache sid hash enable */ 112 113 /* Bits in CPU Diagnose Register 0 */ 114 #define DR0_PCXL_L2IHPMC 6 /* r/c L2 I-cache error flag */ 115 #define DR0_PCXL_L2IHPMC_DIS 7 /* r/w L2 I-cache hpmc disable mask */ 116 #define DR0_PCXL_L2DHPMC 8 /* r/c L2 D-cache error flag */ 117 #define DR0_PCXL_L2DHPMC_DIS 9 /* r/w L2 D-cache hpmc disable mask */ 118 #define DR0_PCXL_L1IHPMC 10 /* r/c L1 I-cache error flag */ 119 #define DR0_PCXL_L1IHPMC_DIS 11 /* r/w L1 I-cache hpmc disable mask */ 120 #define DR0_PCXL_L2PARERR 15 /* r/c L2 Cache parity error (4 bit) */ 121 #define DR0_PCXL_STORE0 16 /* r/w scratch space */ 122 #define DR0_PCXL_PFMASK 17 /* r/w power-fail trap mask */ 123 #define DR0_PCXL_STORE1 18 /* r/w scratch */ 124 #define DR0_PCXL_FASTMODE 19 /* r 0-fast, 1-slow */ 125 #define DR0_PCXL_ISTRM_EN 20 /* r/w I-cache streaming enable */ 126 #define DR0_PCXL_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */ 127 #define DR0_PCXL_ENDIAN 23 /* r/w little endian traps */ 128 #define DR0_PCXL_SOU_EN 24 /* r/w stall-on-use on dc misses */ 129 #define DR0_PCXL_SHINT_EN 25 /* r/w no-fill on miss store hints */ 130 #define DR0_PCXL_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */ 131 #define DR0_PCXL_L2DHASH_EN 27 /* r/w L2 D-cache hash enable */ 132 #define DR0_PCXL_L2IHASH_EN 28 /* r/w L2 I-cache hash enable */ 133 #define DR0_PCXL_L1ICACHE_EN 29 /* r/w L1 I-cache enable */ 134 #define DR0_PCXL_HIT 30 /* r Diag cache read hit indication */ 135 #define DR0_PCXL_PARERR 31 /* r Diag cache read parity error */ 136 137 /* Bits in CPU Diagnose Register 25 */ 138 #define DR25_PCXL_POWFAIL 31 /* r set to 0 by HW on PWR fail */ 139 140 #define DR0_PCXL2_L1DHPMC 8 /* r/c L1 D-cache error flag */ 141 #define DR0_PCXL2_L1DHPMC_DIS 9 /* r/w L1 D-cache hpmc disable */ 142 #define DR0_PCXL2_L2DHPMC 10 /* r/c L1 I-cache error flag */ 143 #define DR0_PCXL2_L2DHPMC_DIS 11 /* r/w L1 I-cache hpmc disable */ 144 #define DR0_PCXL2_SCRATCH 12 /* r/w scratch register */ 145 #define DR0_PCXL2_ACCEL_IO 13 /* /w enable accel IO writes */ 146 #define DR0_PCXL2_STORE0 16 /* r/w scratch space */ 147 #define DR0_PCXL2_PFMASK 17 /* r/w power-fail trap mask */ 148 #define DR0_PCXL2_STORE1 18 /* r/w scratch */ 149 #define DR0_PCXL2_DCSAFE 19 /* r/w serialize all data cache hangs */ 150 #define DR0_PCXL2_ISTRM_EN 20 /* r/w I-cache streaming enable */ 151 #define DR0_PCXL2_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */ 152 #define DR0_PCXL2_ENDIAN 23 /* r/w little endian traps */ 153 #define DR0_PCXL2_SOU_EN 24 /* r/w stall-on-use on dc misses */ 154 #define DR0_PCXL2_SHINT_EN 25 /* r/w no-fill on miss store hints */ 155 #define DR0_PCXL2_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */ 156 #define DR0_PCXL2_LMIN_EN 27 /* r/w minor ill insn traps on LIH */ 157 #define DR0_PCXL2_RMIN_EN 28 /* r/w major ill insn traps on RIH */ 158 #define DR0_PCXL2_L1CACHE_EN 29 /* r/w L1 I-cache enable */ 159 160 #define DR_DTLB 8 161 162 #define DR_ITLB 9 163 164 #define DR0_PCXL2_HTLB_ADDR 24 /* page address of the htlb */ 165 #define DR0_PCXL2_HTLB_CFG 25 /* htlb config */ 166 #define DR0_PCXL2_HTLB_P 0 /* r latches power fail signal */ 167 #define DR0_PCXL2_HTLB_MASK 19 /* w 12bit mask of the hash */ 168 #define DR0_PCXL2_HTLB_FP 26 /* r/w 3bit FP delay */ 169 #define DR0_PCXL2_HTLB_I 28 /* r/w disable ITLB htlb lookup */ 170 #define DR0_PCXL2_HTLB_U 29 /* r/w set cr28 only if tag nomatch */ 171 #define DR0_PCXL2_HTLB_N 30 /* r/w set cr28 from w3 or w7 (0) */ 172 #define DR0_PCXL2_HTLB_D 31 /* r/w disable DTLB htlb lookup */ 173 174 #define DR_ITLB_SIZE_1 24 175 #define DR_ITLB_SIZE_0 25 176 177 #define DR_DTLB_SIZE_1 26 178 #define DR_DTLB_SIZE_0 27 179 180 #define CCR_MASK 0xff 181 182 #define HPPA_NREGS (32) 183 #define HPPA_NFPREGS (33) /* 33rd is used for r0 in fpemul */ 184 185 #ifndef __ASSEMBLER__ 186 187 struct reg { 188 u_int32_t r_regs[HPPA_NREGS]; /* r0 is psw */ 189 190 u_int32_t r_sar; 191 192 u_int32_t r_pcsqh; 193 u_int32_t r_pcsqt; 194 u_int32_t r_pcoqh; 195 u_int32_t r_pcoqt; 196 197 u_int32_t r_sr0; 198 u_int32_t r_sr1; 199 u_int32_t r_sr2; 200 u_int32_t r_sr3; 201 u_int32_t r_sr4; 202 u_int32_t r_sr5; /* !mcontext */ 203 u_int32_t r_sr6; /* !mcontext */ 204 u_int32_t r_sr7; /* !mcontext */ 205 206 u_int32_t r_cr26; 207 u_int32_t r_cr27; 208 }; 209 210 struct fpreg { 211 u_int64_t fpr_regs[HPPA_NFPREGS]; 212 }; 213 #endif /* !__ASSEMBLER__ */ 214 215 #endif /* _HPPA_REG_H_ */ 216