1 /* $NetBSD: mcontext.h,v 1.10 2018/02/27 11:26:39 kamil Exp $ */ 2 3 #ifndef _HPPA_MCONTEXT_H_ 4 #define _HPPA_MCONTEXT_H_ 5 6 /* 7 * General register state 8 */ 9 #define _NGREG 44 10 11 #define _REG_PSW 0 12 #define _REG_RP 2 13 #define _REG_R19 19 14 #define _REG_ARG0 26 15 #define _REG_DP 27 16 #define _REG_RET0 28 17 #define _REG_SP 30 18 #define _REG_SAR 32 19 #define _REG_PCSQH 33 20 #define _REG_PCSQT 34 21 #define _REG_PCOQH 35 22 #define _REG_PCOQT 36 23 #define _REG_SR0 37 24 #define _REG_SR1 38 25 #define _REG_SR2 39 26 #define _REG_SR3 40 27 #define _REG_SR4 41 28 #define _REG_CR26 42 29 #define _REG_CR27 43 30 31 #ifndef __ASSEMBLER__ 32 33 typedef unsigned long __greg_t; 34 typedef __greg_t __gregset_t[_NGREG]; 35 36 /* 37 * Floating point register state 38 */ 39 40 typedef struct { 41 union { 42 unsigned long long __fp_regs[32]; 43 double __fp_dregs[32]; 44 } __fp_fr; 45 } __fpregset_t; 46 47 typedef struct { 48 __gregset_t __gregs; 49 __fpregset_t __fpregs; 50 } mcontext_t; 51 52 #define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP]) 53 #define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[3]) 54 #define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PCOQH]) 55 #define _UC_MACHINE_SET_PC(uc, pc) \ 56 do { \ 57 (uc)->uc_mcontext.__gregs[_REG_PCOQH] = (pc); \ 58 (uc)->uc_mcontext.__gregs[_REG_PCOQT] = (pc) + 4; \ 59 } while (/*CONSTCOND*/0) 60 #define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_RET0]) 61 62 static __inline void * 63 __lwp_getprivate_fast(void) 64 { 65 register void *__tmp; 66 67 __asm volatile("mfctl\t27 /* CR_TLS */, %0" : "=r" (__tmp)); 68 69 return __tmp; 70 } 71 72 #endif /* !__ASSEMBLER__ */ 73 74 #define _UC_SETSTACK 0x00010000 75 #define _UC_CLRSTACK 0x00020000 76 #define _UC_TLSBASE 0x00040000 77 78 #endif /* _HPPA_MCONTEXT_H_ */ 79