1 /* $NetBSD: hd64461pcmcia.c,v 1.38 2007/10/17 19:54:30 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.38 2007/10/17 19:54:30 garbled Exp $"); 41 42 #include "opt_hd64461pcmcia.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/kthread.h> 49 #include <sys/boot_flag.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 65 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 66 67 #include "locators.h" 68 69 #ifdef HD64461PCMCIA_DEBUG 70 #define DPRINTF_ENABLE 71 #define DPRINTF_DEBUG hd64461pcmcia_debug 72 #endif 73 #include <machine/debug.h> 74 75 enum controller_channel { 76 CHANNEL_0 = 0, 77 CHANNEL_1 = 1, 78 CHANNEL_MAX = 2 79 }; 80 81 enum memory_window_mode { 82 MEMWIN_16M_MODE, 83 MEMWIN_32M_MODE 84 }; 85 86 enum memory_window_16 { 87 MEMWIN_16M_COMMON_0, 88 MEMWIN_16M_COMMON_1, 89 MEMWIN_16M_COMMON_2, 90 MEMWIN_16M_COMMON_3, 91 }; 92 #define MEMWIN_16M_MAX 4 93 94 enum memory_window_32 { 95 MEMWIN_32M_ATTR, 96 MEMWIN_32M_COMMON_0, 97 MEMWIN_32M_COMMON_1, 98 }; 99 #define MEMWIN_32M_MAX 3 100 101 enum hd64461pcmcia_event_type { 102 EVENT_NONE, 103 EVENT_INSERT, 104 EVENT_REMOVE, 105 }; 106 #define EVENT_QUEUE_MAX 5 107 108 struct hd64461pcmcia_softc; /* forward declaration */ 109 110 struct hd64461pcmcia_window_cookie { 111 bus_space_tag_t wc_tag; 112 bus_space_handle_t wc_handle; 113 int wc_size; 114 int wc_window; 115 }; 116 117 struct hd64461pcmcia_channel { 118 struct hd64461pcmcia_softc *ch_parent; 119 struct device *ch_pcmcia; 120 enum controller_channel ch_channel; 121 122 /* memory space */ 123 enum memory_window_mode ch_memory_window_mode; 124 bus_space_tag_t ch_memt; 125 bus_space_handle_t ch_memh; 126 bus_addr_t ch_membase_addr; 127 bus_size_t ch_memsize; 128 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 129 130 /* I/O space */ 131 bus_space_tag_t ch_iot; 132 bus_addr_t ch_iobase; 133 bus_size_t ch_iosize; 134 135 /* card interrupt */ 136 int (*ch_ih_card_func)(void *); 137 void *ch_ih_card_arg; 138 int ch_attached; 139 }; 140 141 struct hd64461pcmcia_event { 142 int __queued; 143 enum hd64461pcmcia_event_type pe_type; 144 struct hd64461pcmcia_channel *pe_ch; 145 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 146 }; 147 148 struct hd64461pcmcia_softc { 149 struct device sc_dev; 150 enum hd64461_module_id sc_module_id; 151 int sc_shutdown; 152 153 /* CSC event */ 154 lwp_t *sc_event_thread; 155 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 156 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 157 158 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 159 }; 160 161 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 167 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 176 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 177 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 178 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 181 void *); 182 183 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 184 hd64461pcmcia_chip_mem_alloc, 185 hd64461pcmcia_chip_mem_free, 186 hd64461pcmcia_chip_mem_map, 187 hd64461pcmcia_chip_mem_unmap, 188 hd64461pcmcia_chip_io_alloc, 189 hd64461pcmcia_chip_io_free, 190 hd64461pcmcia_chip_io_map, 191 hd64461pcmcia_chip_io_unmap, 192 hd64461pcmcia_chip_intr_establish, 193 hd64461pcmcia_chip_intr_disestablish, 194 hd64461pcmcia_chip_socket_enable, 195 hd64461pcmcia_chip_socket_disable, 196 hd64461pcmcia_chip_socket_settype, 197 }; 198 199 STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 200 STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 201 STATIC int hd64461pcmcia_print(void *, const char *); 202 STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, 203 const int *, void *); 204 205 CFATTACH_DECL(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 206 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 207 208 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 209 enum controller_channel); 210 /* hot plug */ 211 STATIC void hd64461pcmcia_event_thread(void *); 212 STATIC void queue_event(struct hd64461pcmcia_channel *, 213 enum hd64461pcmcia_event_type); 214 /* interrupt handler */ 215 STATIC int hd64461pcmcia_channel0_intr(void *); 216 STATIC int hd64461pcmcia_channel1_intr(void *); 217 /* card status */ 218 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 219 STATIC void hd64461pcmcia_power_off(enum controller_channel); 220 STATIC void hd64461pcmcia_power_on(enum controller_channel); 221 /* memory window access ops */ 222 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 223 enum memory_window_mode)__attribute__((__unused__)); 224 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 225 enum memory_window_16); 226 /* bus width */ 227 STATIC void hd64461_set_bus_width(enum controller_channel, int); 228 #ifdef HD64461PCMCIA_DEBUG 229 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 230 #endif 231 /* fix SH3 Area[56] bug */ 232 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 233 #define _BUS_SPACE_ACCESS_HOOK() \ 234 do { \ 235 uint8_t dummy __attribute__((__unused__)) = \ 236 *(volatile uint8_t *)0xba000000; \ 237 } while (/*CONSTCOND*/0) 238 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 239 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 240 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 241 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 242 #undef _BUS_SPACE_ACCESS_HOOK 243 244 #define DELAY_MS(x) delay((x) * 1000) 245 246 STATIC int 247 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 248 { 249 struct hd64461_attach_args *ha = aux; 250 251 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 252 } 253 254 STATIC void 255 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 256 { 257 struct hd64461_attach_args *ha = aux; 258 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 259 int error; 260 261 sc->sc_module_id = ha->ha_module_id; 262 263 printf("\n"); 264 265 #ifdef HD64461PCMCIA_DEBUG 266 hd64461pcmcia_info(sc); 267 #endif 268 /* Channel 0/1 common CSC event queue */ 269 SIMPLEQ_INIT (&sc->sc_event_head); 270 error = kthread_create(PRI_NONE, 0, NULL, hd64461pcmcia_event_thread, 271 sc, &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 272 KASSERT(error == 0); 273 274 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 275 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 276 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 277 #else 278 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 279 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 280 #endif 281 } 282 283 STATIC void 284 hd64461pcmcia_event_thread(void *arg) 285 { 286 struct hd64461pcmcia_softc *sc = arg; 287 struct hd64461pcmcia_event *pe; 288 int s; 289 290 while (!sc->sc_shutdown) { 291 tsleep(sc, PWAIT, "CSC wait", 0); 292 s = splhigh(); 293 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 294 splx(s); 295 switch (pe->pe_type) { 296 default: 297 printf("%s: unknown event.\n", __FUNCTION__); 298 break; 299 case EVENT_INSERT: 300 DPRINTF("insert event.\n"); 301 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 302 break; 303 case EVENT_REMOVE: 304 DPRINTF("remove event.\n"); 305 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 306 DETACH_FORCE); 307 break; 308 } 309 s = splhigh(); 310 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 311 pe->__queued = 0; 312 } 313 splx(s); 314 } 315 /* NOTREACHED */ 316 } 317 318 STATIC int 319 hd64461pcmcia_print(void *arg, const char *pnp) 320 { 321 322 if (pnp) 323 aprint_normal("pcmcia at %s", pnp); 324 325 return (UNCONF); 326 } 327 328 STATIC int 329 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, 330 const int *ldesc, void *aux) 331 { 332 struct pcmciabus_attach_args *paa = aux; 333 struct hd64461pcmcia_channel *ch = 334 (struct hd64461pcmcia_channel *)paa->pch; 335 336 if (ch->ch_channel == CHANNEL_0) { 337 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 338 PCMCIABUSCF_CONTROLLER_DEFAULT && 339 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 340 return 0; 341 } else { 342 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 343 PCMCIABUSCF_CONTROLLER_DEFAULT && 344 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 345 return 0; 346 } 347 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 348 349 return (config_match(parent, cf, aux)); 350 } 351 352 STATIC void 353 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 354 enum controller_channel channel) 355 { 356 struct device *parent = (struct device *)sc; 357 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 358 struct pcmciabus_attach_args paa; 359 bus_addr_t membase; 360 int i; 361 362 ch->ch_parent = sc; 363 ch->ch_channel = channel; 364 365 /* 366 * Continuous 16-MB Area Mode 367 */ 368 /* Attibute/Common memory extent */ 369 membase = (channel == CHANNEL_0) 370 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 371 372 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 373 membase, 0x01000000); /* 16MB */ 374 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 375 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 376 &ch->ch_memh); 377 fixup_sh3_pcmcia_area(ch->ch_memt); 378 379 /* Common memory space extent */ 380 ch->ch_memsize = 0x01000000; 381 for (i = 0; i < MEMWIN_16M_MAX; i++) { 382 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 383 membase + 0x01000000, 384 ch->ch_memsize); 385 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 386 } 387 388 /* I/O port extent and interrupt staff */ 389 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 390 391 if (channel == CHANNEL_0) { 392 ch->ch_iobase = 0; 393 ch->ch_iosize = HD64461_PCC0_IOSIZE; 394 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 395 HD64461_PCC0_IOBASE, 396 ch->ch_iosize); 397 fixup_sh3_pcmcia_area(ch->ch_iot); 398 399 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 400 hd64461pcmcia_channel0_intr, ch); 401 } else { 402 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 403 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 404 hd64461pcmcia_channel1_intr, ch); 405 } 406 407 paa.paa_busname = "pcmcia"; 408 paa.pch = (pcmcia_chipset_handle_t)ch; 409 paa.iobase = ch->ch_iobase; 410 paa.iosize = ch->ch_iosize; 411 412 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 413 hd64461pcmcia_print, hd64461pcmcia_submatch); 414 415 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 416 ch->ch_attached = 1; 417 pcmcia_card_attach(ch->ch_pcmcia); 418 } 419 } 420 421 STATIC int 422 hd64461pcmcia_channel0_intr(void *arg) 423 { 424 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 425 uint8_t r; 426 int ret = 0; 427 428 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 429 /* clear interrtupt (edge source only) */ 430 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 431 432 if (r & HD64461_PCC0CSCR_P0IREQ) { 433 if (ch->ch_ih_card_func) { 434 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 435 } else 436 DPRINTF("spurious IREQ interrupt.\n"); 437 } 438 439 if (r & HD64461_PCC0CSCR_P0CDC) 440 queue_event(ch, detect_card(ch->ch_channel)); 441 442 return ret; 443 } 444 445 STATIC int 446 hd64461pcmcia_channel1_intr(void *arg) 447 { 448 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 449 uint8_t r; 450 int ret = 0; 451 452 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 453 /* clear interrtupt */ 454 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 455 456 if (r & HD64461_PCC1CSCR_P1RC) { 457 if (ch->ch_ih_card_func) 458 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 459 else 460 DPRINTF("spurious READY interrupt.\n"); 461 } 462 463 if (r & HD64461_PCC1CSCR_P1CDC) 464 queue_event(ch, detect_card(ch->ch_channel)); 465 466 return ret; 467 } 468 469 STATIC void 470 queue_event(struct hd64461pcmcia_channel *ch, 471 enum hd64461pcmcia_event_type type) 472 { 473 struct hd64461pcmcia_event *pe, *pool; 474 struct hd64461pcmcia_softc *sc = ch->ch_parent; 475 int i; 476 int s = splhigh(); 477 478 if (type == EVENT_NONE) 479 goto out; 480 481 pe = 0; 482 pool = sc->sc_event_pool; 483 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 484 if (!pool[i].__queued) { 485 pe = &pool[i]; 486 break; 487 } 488 } 489 490 if (pe == 0) { 491 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 492 EVENT_QUEUE_MAX); 493 goto out; 494 } 495 496 if ((ch->ch_attached && (type == EVENT_INSERT)) || 497 (!ch->ch_attached && (type == EVENT_REMOVE))) { 498 DPRINTF("spurious CSC interrupt.\n"); 499 goto out; 500 } 501 502 ch->ch_attached = (type == EVENT_INSERT); 503 pe->__queued = 1; 504 pe->pe_type = type; 505 pe->pe_ch = ch; 506 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 507 wakeup(sc); 508 out: 509 splx(s); 510 } 511 512 /* 513 * interface for pcmcia driver. 514 */ 515 STATIC void * 516 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 517 struct pcmcia_function *pf, 518 int ipl, int (*ih_func)(void *), void *ih_arg) 519 { 520 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 521 int channel = ch->ch_channel; 522 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 523 int s = splhigh(); 524 uint8_t r; 525 526 ch->ch_ih_card_func = ih_func; 527 ch->ch_ih_card_arg = ih_arg; 528 529 /* enable card interrupt */ 530 r = hd64461_reg_read_1(cscier); 531 if (channel == CHANNEL_0) { 532 /* set level mode */ 533 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 534 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 535 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 536 } else { 537 /* READY-pin LOW to HIGH changes generates interrupt */ 538 r |= HD64461_PCC1CSCIER_P1RE; 539 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 540 } 541 hd64461_reg_write_1(cscier, r); 542 543 splx(s); 544 545 return (void *)ih_func; 546 } 547 548 STATIC void 549 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 550 { 551 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 552 int channel = ch->ch_channel; 553 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 554 int s = splhigh(); 555 uint8_t r; 556 557 /* disable card interrupt */ 558 r = hd64461_reg_read_1(cscier); 559 if (channel == CHANNEL_0) { 560 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 561 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 562 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 563 } else { 564 r &= ~HD64461_PCC1CSCIER_P1RE; 565 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 566 } 567 hd64461_reg_write_1(cscier, r); 568 569 ch->ch_ih_card_func = 0; 570 571 splx(s); 572 } 573 574 STATIC int 575 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 576 struct pcmcia_mem_handle *pcmhp) 577 { 578 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 579 580 pcmhp->memt = ch->ch_memt; 581 pcmhp->addr = ch->ch_membase_addr; 582 pcmhp->memh = ch->ch_memh; 583 pcmhp->size = size; 584 pcmhp->realsize = size; 585 586 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 587 588 return (0); 589 } 590 591 STATIC void 592 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 593 struct pcmcia_mem_handle *pcmhp) 594 { 595 /* nothing to do */ 596 } 597 598 STATIC int 599 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 600 bus_addr_t card_addr, 601 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 602 bus_size_t *offsetp, int *windowp) 603 { 604 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 605 struct hd64461pcmcia_window_cookie *cookie; 606 bus_addr_t ofs; 607 608 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 609 M_DEVBUF, M_NOWAIT); 610 KASSERT(cookie); 611 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 612 613 /* Address */ 614 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 615 cookie->wc_tag = ch->ch_memt; 616 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 617 size, &cookie->wc_handle) != 0) 618 goto bad; 619 620 *offsetp = card_addr; 621 cookie->wc_window = -1; 622 } else { 623 int window = card_addr / ch->ch_memsize; 624 KASSERT(window < MEMWIN_16M_MAX); 625 626 cookie->wc_tag = ch->ch_cmemt[window]; 627 ofs = card_addr - window * ch->ch_memsize; 628 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 629 &cookie->wc_handle) != 0) 630 goto bad; 631 632 /* XXX bogus. check window per common memory access. */ 633 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 634 *offsetp = ofs + 0x01000000; /* skip attribute area */ 635 cookie->wc_window = window; 636 } 637 cookie->wc_size = size; 638 *windowp = (int)cookie; 639 640 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 641 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 642 size); 643 644 return (0); 645 bad: 646 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 647 free(cookie, M_DEVBUF); 648 649 return (1); 650 } 651 652 STATIC void 653 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 654 { 655 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 656 657 if (cookie->wc_window != -1) 658 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 659 cookie->wc_size); 660 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 661 free(cookie, M_DEVBUF); 662 } 663 664 STATIC int 665 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 666 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 667 { 668 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 669 670 if (ch->ch_channel == CHANNEL_1) 671 return (1); 672 673 if (start) { 674 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 675 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 676 return (1); 677 } 678 DPRINTF("map %#lx+%#lx\n", start, size); 679 } else { 680 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 681 ch->ch_iobase + ch->ch_iosize - 1, 682 size, align, 0, 0, &pcihp->addr, 683 &pcihp->ioh)) { 684 DPRINTF("couldn't allocate %#lx\n", size); 685 return (1); 686 } 687 pcihp->flags = PCMCIA_IO_ALLOCATED; 688 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 689 } 690 691 pcihp->iot = ch->ch_iot; 692 pcihp->size = size; 693 694 return (0); 695 } 696 697 STATIC int 698 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 699 bus_addr_t offset, 700 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 701 { 702 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 703 #ifdef HD64461PCMCIA_DEBUG 704 static const char *width_names[] = { "auto", "io8", "io16" }; 705 #endif 706 if (ch->ch_channel == CHANNEL_1) 707 return (1); 708 709 hd64461_set_bus_width(CHANNEL_0, width); 710 711 /* fake. drivers init that to -1 and check if it was changed. */ 712 *windowp = 0; 713 714 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 715 width_names[width]); 716 717 return (0); 718 } 719 720 STATIC void 721 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 722 struct pcmcia_io_handle *pcihp) 723 { 724 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 725 726 if (ch->ch_channel == CHANNEL_1) 727 return; 728 729 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 730 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 731 else 732 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 733 734 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 735 } 736 737 STATIC void 738 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 739 { 740 741 /* nothing to do */ 742 } 743 744 STATIC void 745 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 746 { 747 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 748 int channel = ch->ch_channel; 749 bus_addr_t isr, gcr; 750 uint8_t r; 751 int i; 752 753 DPRINTF("enable channel %d\n", channel); 754 isr = HD64461_PCCISR(channel); 755 gcr = HD64461_PCCGCR(channel); 756 757 hd64461pcmcia_power_off(channel); 758 hd64461pcmcia_power_on(channel); 759 760 /* assert reset, set card type to memory */ 761 r = hd64461_reg_read_1(gcr); 762 r |= HD64461_PCCGCR_PCCR; 763 r &= ~HD64461_PCC0GCR_P0PCCT; 764 hd64461_reg_write_1(gcr, r); 765 766 /* 767 * hold RESET at least 10us. 768 */ 769 DELAY_MS(20); 770 771 /* clear the reset flag */ 772 r &= ~HD64461_PCCGCR_PCCR; 773 hd64461_reg_write_1(gcr, r); 774 DELAY_MS(2000); 775 776 /* wait for the chip to finish initializing */ 777 for (i = 0; i < 10000; i++) { 778 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 779 goto reset_ok; 780 DELAY_MS(500); 781 782 if ((i > 5000) && (i % 100 == 99)) 783 printf("."); 784 } 785 printf("reset failed.\n"); 786 hd64461pcmcia_power_off(channel); 787 return; 788 789 reset_ok: 790 /* set Continuous 16-MB Area Mode */ 791 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 792 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 793 794 /* 795 * set Common memory area. 796 */ 797 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 798 799 DPRINTF("OK.\n"); 800 } 801 802 STATIC void 803 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 804 { 805 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 806 int channel = ch->ch_channel; 807 bus_addr_t gcr; 808 uint8_t r; 809 810 DPRINTF("settype channel %d\n", channel); 811 gcr = HD64461_PCCGCR(channel); 812 813 /* set the card type */ 814 r = hd64461_reg_read_1(gcr); 815 if (channel == CHANNEL_0) { 816 if (type == PCMCIA_IFTYPE_IO) 817 r |= HD64461_PCC0GCR_P0PCCT; 818 else 819 r &= ~HD64461_PCC0GCR_P0PCCT; 820 } else { 821 /* reserved bit must be 0 */ 822 r &= ~HD64461_PCC1GCR_RESERVED; 823 } 824 hd64461_reg_write_1(gcr, r); 825 826 DPRINTF("OK.\n"); 827 } 828 829 STATIC void 830 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 831 { 832 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 833 int channel = ch->ch_channel; 834 835 /* dont' disable CSC interrupt */ 836 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 837 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 838 839 /* power down the socket */ 840 hd64461pcmcia_power_off(channel); 841 } 842 843 /* 844 * Card detect 845 */ 846 STATIC void 847 hd64461pcmcia_power_off(enum controller_channel channel) 848 { 849 uint8_t r; 850 uint16_t r16; 851 bus_addr_t scr, gcr; 852 853 gcr = HD64461_PCCGCR(channel); 854 scr = HD64461_PCCSCR(channel); 855 856 /* DRV (external buffer) high level */ 857 r = hd64461_reg_read_1(gcr); 858 r &= ~HD64461_PCCGCR_DRVE; 859 hd64461_reg_write_1(gcr, r); 860 861 /* stop power */ 862 r = hd64461_reg_read_1(scr); 863 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 864 hd64461_reg_write_1(scr, r); 865 r = hd64461_reg_read_1(gcr); 866 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 867 hd64461_reg_write_1(gcr, r); 868 /* 869 * wait 300ms until power fails (Tpf). Then, wait 100ms since 870 * we are changing Vcc (Toff). 871 */ 872 DELAY_MS(300 + 100); 873 874 /* stop clock */ 875 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 876 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 877 HD64461_SYSSTBCR_SPC1ST); 878 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 879 } 880 881 STATIC void 882 hd64461pcmcia_power_on(enum controller_channel channel) 883 { 884 uint8_t r; 885 uint16_t r16; 886 bus_addr_t scr, gcr, isr; 887 888 isr = HD64461_PCCISR(channel); 889 gcr = HD64461_PCCGCR(channel); 890 scr = HD64461_PCCSCR(channel); 891 892 /* 893 * XXX to access attribute memory, this is required. 894 */ 895 if (channel == CHANNEL_0) { 896 /* GPIO Port A XXX Jonanada690 specific? */ 897 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 898 r16 &= ~0xf; 899 r16 |= 0x5; 900 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 901 } 902 903 if (channel == CHANNEL_1) { 904 /* GPIO Port C, Port D -> PCC1 pin 905 * I assume SYSCR[1:0] == 0 906 */ 907 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 908 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 909 } 910 911 /* supply clock */ 912 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 913 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 914 HD64461_SYSSTBCR_SPC1ST); 915 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 916 DELAY_MS(200); 917 918 /* detect voltage and supply VCC */ 919 r = hd64461_reg_read_1(isr); 920 921 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 922 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 923 DPRINTF("5V card\n"); 924 hd64461pcmcia_power(channel, V_5, 1); 925 break; 926 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 927 /* FALLTHROUGH */ 928 case 0: /* x.x / 3.3 / 5 V */ 929 DPRINTF("3.3V card\n"); 930 hd64461pcmcia_power(channel, V_3_3, 1); 931 break; 932 case HD64461_PCCISR_VS1: /* x.x V */ 933 /* FALLTHROUGH */ 934 DPRINTF("x.x V card\n"); 935 hd64461pcmcia_power(channel, V_X_X, 1); 936 return; 937 default: 938 printf("\nunknown Voltage. don't attach.\n"); 939 return; 940 } 941 942 /* 943 * wait 100ms until power raise (Tpr) and 20ms to become 944 * stable (Tsu(Vcc)). 945 * 946 * some machines require some more time to be settled 947 * (300ms is added here). 948 */ 949 DELAY_MS(100 + 20 + 300); 950 951 /* DRV (external buffer) low level */ 952 r = hd64461_reg_read_1(gcr); 953 r |= HD64461_PCCGCR_DRVE; 954 hd64461_reg_write_1(gcr, r); 955 956 /* clear interrupt */ 957 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 958 HD64461_PCC1CSCR_REG8, 0); 959 } 960 961 STATIC enum hd64461pcmcia_event_type 962 detect_card(enum controller_channel channel) 963 { 964 uint8_t r; 965 966 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 967 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 968 969 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 970 DPRINTF("remove\n"); 971 return EVENT_REMOVE; 972 } 973 if (r == 0) { 974 DPRINTF("insert\n"); 975 return EVENT_INSERT; 976 } 977 DPRINTF("transition\n"); 978 979 return EVENT_NONE; 980 } 981 982 /* 983 * Memory window access ops. 984 */ 985 STATIC void 986 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 987 enum memory_window_mode mode) 988 { 989 bus_addr_t a = HD64461_PCCGCR(channel); 990 uint8_t r = hd64461_reg_read_1(a); 991 992 r &= ~HD64461_PCCGCR_MMOD; 993 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 994 HD64461_PCCGCR_MMOD_32M; 995 hd64461_reg_write_1(a, r); 996 } 997 998 STATIC void 999 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1000 enum memory_window_16 window) 1001 { 1002 bus_addr_t a = HD64461_PCCGCR(channel); 1003 uint8_t r; 1004 1005 r = hd64461_reg_read_1(a); 1006 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1007 1008 switch (window) { 1009 case MEMWIN_16M_COMMON_0: 1010 break; 1011 case MEMWIN_16M_COMMON_1: 1012 r |= HD64461_PCCGCR_PA24; 1013 break; 1014 case MEMWIN_16M_COMMON_2: 1015 r |= HD64461_PCCGCR_PA25; 1016 break; 1017 case MEMWIN_16M_COMMON_3: 1018 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1019 break; 1020 } 1021 1022 hd64461_reg_write_1(a, r); 1023 } 1024 1025 #if unused 1026 STATIC void 1027 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1028 { 1029 bus_addr_t a = HD64461_PCCGCR(channel); 1030 uint8_t r; 1031 1032 r = hd64461_reg_read_1(a); 1033 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1034 1035 switch (window) { 1036 case MEMWIN_32M_ATTR: 1037 break; 1038 case MEMWIN_32M_COMMON_0: 1039 r |= HD64461_PCCGCR_PREG; 1040 break; 1041 case MEMWIN_32M_COMMON_1: 1042 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1043 break; 1044 } 1045 1046 hd64461_reg_write_1(a, r); 1047 } 1048 #endif 1049 1050 STATIC void 1051 hd64461_set_bus_width(enum controller_channel channel, int width) 1052 { 1053 uint16_t r16; 1054 1055 r16 = _reg_read_2(SH3_BCR2); 1056 if (channel == CHANNEL_0) { 1057 r16 &= ~((1 << 13)|(1 << 12)); 1058 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1059 } else { 1060 r16 &= ~((1 << 11)|(1 << 10)); 1061 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1062 } 1063 _reg_write_2(SH3_BCR2, r16); 1064 } 1065 1066 STATIC void 1067 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1068 { 1069 struct hpcsh_bus_space *hbs = (void *)t; 1070 1071 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1072 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1073 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1074 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1075 } 1076 1077 #ifdef HD64461PCMCIA_DEBUG 1078 STATIC void 1079 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1080 { 1081 uint8_t r8; 1082 1083 dbg_banner_function(); 1084 /* 1085 * PCC0 1086 */ 1087 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1088 printf("PCC0 Interface Status Register\n"); 1089 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1090 1091 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1092 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1093 _(P0BVD2);_(P0BVD1); 1094 #undef _ 1095 printf("\n"); 1096 1097 printf("PCC0 General Control Register\n"); 1098 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1099 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1100 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1101 _(P0PA25);_(P0PA24);_(P0REG); 1102 #undef _ 1103 printf("\n"); 1104 1105 printf("PCC0 Card Status Change Register\n"); 1106 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1107 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1108 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1109 #undef _ 1110 printf("\n"); 1111 1112 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1113 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1114 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1115 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1116 #undef _ 1117 printf("\ninterrupt type: "); 1118 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1119 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1120 printf("none\n"); 1121 break; 1122 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1123 printf("level\n"); 1124 break; 1125 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1126 printf("falling edge\n"); 1127 break; 1128 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1129 printf("rising edge\n"); 1130 break; 1131 } 1132 1133 printf("PCC0 Software Control Register\n"); 1134 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1135 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1136 _(P0VCC1);_(P0SWP); 1137 #undef _ 1138 printf("\n"); 1139 1140 /* 1141 * PCC1 1142 */ 1143 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1144 printf("PCC1 Interface Status Register\n"); 1145 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1146 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1147 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1148 _(P1BVD2);_(P1BVD1); 1149 #undef _ 1150 printf("\n"); 1151 1152 printf("PCC1 General Contorol Register\n"); 1153 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1154 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1155 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1156 #undef _ 1157 printf("\n"); 1158 1159 printf("PCC1 Card Status Change Register\n"); 1160 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1161 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1162 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1163 #undef _ 1164 printf("\n"); 1165 1166 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1167 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1168 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1169 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1170 #undef _ 1171 printf("\n"); 1172 1173 printf("PCC1 Software Control Register\n"); 1174 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1175 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1176 _(P1VCC1);_(P1SWP); 1177 #undef _ 1178 printf("\n"); 1179 1180 /* 1181 * General Control 1182 */ 1183 printf("[General Control]\n"); 1184 printf("PCC0 Output pins Control Register\n"); 1185 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1186 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1187 _(P0DEPLUP);_(P0AEPLUP); 1188 #undef _ 1189 printf("\n"); 1190 1191 printf("PCC1 Output pins Control Register\n"); 1192 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1193 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1194 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1195 #undef _ 1196 printf("\n"); 1197 1198 printf("PC Card General Control Register\n"); 1199 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1200 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1201 _(PSSDIR);_(PSSRDWR); 1202 #undef _ 1203 printf("\n"); 1204 1205 dbg_banner_line(); 1206 } 1207 #endif /* HD64461PCMCIA_DEBUG */ 1208