1 /* $NetBSD: vr4181aiu.c,v 1.9 2014/03/16 05:20:24 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: vr4181aiu.c,v 1.9 2014/03/16 05:20:24 dholland Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/malloc.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 43 #include <mips/cpuregs.h> 44 45 #include <machine/bus.h> 46 47 #include <hpcmips/vr/vripif.h> 48 #include <hpcmips/vr/vr4181aiureg.h> 49 #include <hpcmips/vr/vr4181dcureg.h> 50 51 #define INBUFLEN 1024 /* length in u_int16_t */ 52 #define INPUTLEN 1000 53 #define SAMPLEFREQ 1000 54 #define PICKUPFREQ 100 55 #define PICKUPCOUNT (SAMPLEFREQ / PICKUPFREQ) 56 57 #define ST_BUSY 0x01 58 #define ST_OVERRUN 0x02 59 60 #define INBUF_MASK 0x3ff /* 2Kbyte */ 61 #define INBUF_RAW_SIZE (INBUFLEN * 4 + (INBUF_MASK + 1)) 62 63 #ifdef VR4181AIU_DEBUG 64 int vr4181aiu_debug = 0; 65 #define DPRINTF(x) if (vr4181aiu_debug) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 71 struct vr4181aiu_softc { 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_dcu1_ioh; 74 bus_space_handle_t sc_dcu2_ioh; 75 bus_space_handle_t sc_aiu_ioh; 76 u_int16_t *sc_inbuf_head; 77 u_int16_t *sc_inbuf_tail; 78 u_int16_t *sc_inbuf_which; 79 u_int16_t *sc_inbuf1; 80 u_int16_t *sc_inbuf2; 81 u_int16_t *sc_inbuf_raw; 82 int sc_status; 83 }; 84 85 static int vr4181aiu_match(device_t, cfdata_t, void *); 86 static void vr4181aiu_attach(device_t, device_t, void *); 87 static int vr4181aiu_intr(void *); 88 89 extern struct cfdriver vr4181aiu_cd; 90 91 CFATTACH_DECL_NEW(vr4181aiu, sizeof(struct vr4181aiu_softc), 92 vr4181aiu_match, vr4181aiu_attach, NULL, NULL); 93 94 dev_type_open(vr4181aiuopen); 95 dev_type_close(vr4181aiuclose); 96 dev_type_read(vr4181aiuread); 97 dev_type_write(vr4181aiuwrite); 98 99 const struct cdevsw vr4181aiu_cdevsw = { 100 .d_open = vr4181aiuopen, 101 .d_close = vr4181aiuclose, 102 .d_read = vr4181aiuread, 103 .d_write = vr4181aiuwrite, 104 .d_ioctl = noioctl, 105 .d_stop = nostop, 106 .d_tty = notty, 107 .d_poll = nopoll, 108 .d_mmap = nommap, 109 .d_kqfilter = nokqfilter, 110 .d_flag = 0 111 }; 112 113 static int 114 vr4181aiu_match(device_t parent, cfdata_t cf, void *aux) 115 { 116 return 1; 117 } 118 119 static void 120 vr4181aiu_init_inbuf(struct vr4181aiu_softc *sc) 121 { 122 /* 123 * XXXXXXXXXXXXXXXXX 124 * 125 * this is just a quick and dirty hack to locate the buffer 126 * in KSEG0 space. the only reason is that i want the physical 127 * address of the buffer. 128 * 129 * bus_dma framework should be used. 130 */ 131 static char inbufbase[INBUF_RAW_SIZE]; 132 133 sc->sc_inbuf_raw = (u_int16_t *) inbufbase; 134 135 sc->sc_inbuf1 = (u_int16_t *) ((((u_int32_t) sc->sc_inbuf_raw) 136 + INBUF_MASK) 137 & ~INBUF_MASK); 138 sc->sc_inbuf2 = sc->sc_inbuf1 + INBUFLEN; 139 } 140 141 static void 142 vr4181aiu_disable(struct vr4181aiu_softc *sc) 143 { 144 /* irq clear */ 145 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 146 DCU_DMAITRQ_REG_W, DCU_MICEOP); 147 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 148 VR4181AIU_INT_REG_W, 149 VR4181AIU_MIDLEINTR 150 | VR4181AIU_MSTINTR 151 | VR4181AIU_SIDLEINTR); 152 153 /* disable microphone */ 154 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 155 VR4181AIU_SEQ_REG_W, 0); 156 157 /* disable ADC */ 158 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 159 VR4181AIU_MCNT_REG_W, 0); 160 161 /* disable DMA */ 162 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 163 DCU_AIUDMAMSK_REG_W, 0); 164 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 165 DCU_DMAITMK_REG_W, 0); 166 167 sc->sc_status = 0; 168 } 169 170 static void 171 vr4181aiu_attach(device_t parent, device_t self, void *aux) 172 { 173 struct vrip_attach_args *va = aux; 174 struct vr4181aiu_softc *sc = device_private(self); 175 176 vr4181aiu_init_inbuf(sc); 177 memset(sc->sc_inbuf1, 0x55, INBUFLEN * 2); 178 memset(sc->sc_inbuf2, 0xaa, INBUFLEN * 2); 179 180 sc->sc_status = 0; 181 sc->sc_iot = va->va_iot; 182 183 if (bus_space_map(sc->sc_iot, 184 VR4181AIU_DCU1_BASE, VR4181AIU_DCU1_SIZE, 185 0, &sc->sc_dcu1_ioh)) 186 goto out_dcu1; 187 if (bus_space_map(sc->sc_iot, 188 VR4181AIU_DCU2_BASE, VR4181AIU_DCU2_SIZE, 189 0, &sc->sc_dcu2_ioh)) 190 goto out_dcu2; 191 if (bus_space_map(sc->sc_iot, 192 VR4181AIU_AIU_BASE, VR4181AIU_AIU_SIZE, 193 0, &sc->sc_aiu_ioh)) 194 goto out_aiu; 195 196 /* 197 * reset AIU 198 */ 199 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 200 VR4181AIU_SEQ_REG_W, VR4181AIU_AIURST); 201 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 202 VR4181AIU_SEQ_REG_W, 0); 203 204 /* 205 * set sample rate (1kHz fixed) 206 * XXXX 207 * assume to PCLK is 32.768MHz 208 */ 209 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 210 VR4181AIU_MCNVC_END, 211 32768000 / SAMPLEFREQ); 212 213 /* 214 * XXXX 215 * assume to PCLK is 32.768MHz 216 * DAVREF_SETUP = 5usec * PCLK = 163.84 217 */ 218 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 219 VR4181AIU_DAVREF_SETUP_REG_W, 164); 220 221 vr4181aiu_disable(sc); 222 223 if (vrip_intr_establish(va->va_vc, va->va_unit, 0, 224 IPL_BIO, vr4181aiu_intr, sc) == NULL) { 225 printf("%s: can't establish interrupt\n", 226 device_xname(self)); 227 return; 228 } 229 230 printf("\n"); 231 return; 232 233 out_aiu: 234 bus_space_unmap(sc->sc_iot, sc->sc_dcu2_ioh, VR4181AIU_DCU2_SIZE); 235 out_dcu2: 236 bus_space_unmap(sc->sc_iot, sc->sc_dcu1_ioh, VR4181AIU_DCU1_SIZE); 237 out_dcu1: 238 printf(": can't map i/o space\n"); 239 } 240 241 int 242 vr4181aiuopen(dev_t dev, int flag, int mode, struct lwp *l) 243 { 244 struct vr4181aiu_softc *sc; 245 246 sc = device_lookup_private(&vr4181aiu_cd, minor(dev)); 247 if (sc == NULL) 248 return ENXIO; 249 250 if (sc->sc_status & ST_BUSY) 251 return EBUSY; 252 253 sc->sc_inbuf_head = sc->sc_inbuf_tail 254 = sc->sc_inbuf_which = sc->sc_inbuf1; 255 sc->sc_status &= ~ST_OVERRUN; 256 257 /* setup DMA */ 258 /* reset */ 259 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 260 DCU_DMARST_REG_W, 0); 261 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 262 DCU_DMARST_REG_W, DCU_DMARST); 263 /* dest1 <- sc_inbuf1 */ 264 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 265 DCU_MICDEST1REG1_W, 266 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) & 0xffff); 267 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 268 DCU_MICDEST1REG2_W, 269 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) >> 16); 270 /* dest2 <- sc_inbuf2 */ 271 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 272 DCU_MICDEST2REG1_W, 273 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) & 0xffff); 274 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 275 DCU_MICDEST2REG2_W, 276 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) >> 16); 277 /* record length <- INPUTLEN */ 278 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 279 DCU_MICRCLEN_REG_W, INPUTLEN); 280 /* config <- auto load */ 281 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 282 DCU_MICDMACFG_REG_W, DCU_MICLOAD); 283 /* irq <- irq clear */ 284 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 285 DCU_DMAITRQ_REG_W, DCU_MICEOP); 286 /* control <- INC */ 287 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 288 DCU_DMACTL_REG_W, DCU_MICCNT_INC); 289 /* irq mask <- microphone end of process */ 290 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 291 DCU_DMAITMK_REG_W, DCU_MICEOP_ENABLE); 292 293 /* enable DMA */ 294 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 295 DCU_AIUDMAMSK_REG_W, DCU_ENABLE_MIC); 296 297 /* enable ADC */ 298 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 299 VR4181AIU_MCNT_REG_W, VR4181AIU_ADENAIU); 300 301 /* enable microphone */ 302 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 303 VR4181AIU_SEQ_REG_W, VR4181AIU_AIUMEN); 304 305 sc->sc_status |= ST_BUSY; 306 307 return 0; 308 } 309 310 int 311 vr4181aiuclose(dev_t dev, int flag, int mode, struct lwp *l) 312 { 313 vr4181aiu_disable(device_lookup_private(&vr4181aiu_cd, minor(dev))); 314 return 0; 315 } 316 317 int 318 vr4181aiuread(dev_t dev, struct uio *uio, int flag) 319 { 320 struct vr4181aiu_softc *sc; 321 int s; 322 u_int16_t *fence; 323 int avail; 324 int count; 325 u_int8_t tmp[INPUTLEN / PICKUPCOUNT]; 326 u_int16_t *src; 327 u_int8_t *dst; 328 329 sc = device_lookup_private(&vr4181aiu_cd, minor(dev)); 330 331 src = sc->sc_inbuf_tail; 332 s = splbio(); 333 if (src == sc->sc_inbuf_head) { 334 /* wait for DMA to complete writing */ 335 tsleep(sc, PRIBIO, "aiu read", 0); 336 /* now sc_inbuf_head points alternate buffer */ 337 } 338 splx(s); 339 340 fence = sc->sc_inbuf_which == sc->sc_inbuf1 341 ? &sc->sc_inbuf1[INPUTLEN] 342 : &sc->sc_inbuf2[INPUTLEN]; 343 avail = (fence - src) / PICKUPCOUNT; 344 count = min(avail, uio->uio_resid); 345 dst = tmp; 346 while (count > 0) { 347 *dst++ = (u_int8_t) (*src >> 2); 348 src += PICKUPCOUNT; 349 count--; 350 } 351 352 if (src < fence) { 353 sc->sc_inbuf_tail = src; 354 } else { 355 /* alter the buffer */ 356 sc->sc_inbuf_tail 357 = sc->sc_inbuf_which 358 = sc->sc_inbuf_which == sc->sc_inbuf1 359 ? sc->sc_inbuf2 : sc->sc_inbuf1; 360 } 361 362 return uiomove(tmp, dst - tmp, uio); 363 } 364 365 int 366 vr4181aiuwrite(dev_t dev, struct uio *uio, int flag) 367 { 368 return 0; 369 } 370 371 /* 372 * interrupt handler 373 */ 374 static int 375 vr4181aiu_intr(void *arg) 376 { 377 struct vr4181aiu_softc *sc = arg; 378 379 if (!(sc->sc_status & ST_BUSY)) { 380 printf("vr4181aiu_intr: stray interrupt\n"); 381 vr4181aiu_disable(sc); 382 return 0; 383 } 384 385 /* irq clear */ 386 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 387 DCU_DMAITRQ_REG_W, DCU_MICEOP); 388 389 if (sc->sc_inbuf_head == sc->sc_inbuf1) { 390 if (sc->sc_inbuf_tail != sc->sc_inbuf1) 391 sc->sc_status |= ST_OVERRUN; 392 sc->sc_inbuf_head = sc->sc_inbuf2; 393 } else { 394 if (sc->sc_inbuf_tail != sc->sc_inbuf2) 395 sc->sc_status |= ST_OVERRUN; 396 sc->sc_inbuf_head = sc->sc_inbuf1; 397 } 398 399 if (sc->sc_status & ST_OVERRUN) { 400 printf("vr4181aiu_intr: overrun\n"); 401 } 402 403 DPRINTF(("vr4181aiu_intr: sc_inbuf1 = %04x, sc_inbuf2 = %04x\n", 404 sc->sc_inbuf1[0], sc->sc_inbuf2[0])); 405 406 wakeup(sc); 407 408 return 0; 409 } 410