1 /* $NetBSD: rtc.c,v 1.24 2006/09/16 02:14:57 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Shin Takemura. All rights reserved. 5 * Copyright (c) 1999 SATO Kazumi. All rights reserved. 6 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: rtc.c,v 1.24 2006/09/16 02:14:57 gdamore Exp $"); 40 41 #include "opt_vr41xx.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/timetc.h> 46 47 #include <machine/sysconf.h> 48 #include <machine/bus.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <hpcmips/vr/vr.h> 53 #include <hpcmips/vr/vrcpudef.h> 54 #include <hpcmips/vr/vripif.h> 55 #include <hpcmips/vr/vripreg.h> 56 #include <hpcmips/vr/rtcreg.h> 57 58 /* 59 * for debugging definitions 60 * VRRTCDEBUG print rtc debugging information 61 */ 62 #ifdef VRRTCDEBUG 63 #ifndef VRRTCDEBUG_CONF 64 #define VRRTCDEBUG_CONF 0 65 #endif 66 int vrrtc_debug = VRRTCDEBUG_CONF; 67 #define DPRINTF(arg) if (vrrtc_debug) printf arg; 68 #define DDUMP_REGS(arg) if (vrrtc_debug) vrrtc_dump_regs(arg); 69 #else /* VRRTCDEBUG */ 70 #define DPRINTF(arg) 71 #define DDUMP_REGS(arg) 72 #endif /* VRRTCDEBUG */ 73 74 struct vrrtc_softc { 75 struct device sc_dev; 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 void *sc_ih; 79 #ifndef SINGLE_VRIP_BASE 80 int sc_rtcint_reg; 81 int sc_tclk_h_reg, sc_tclk_l_reg; 82 int sc_tclk_cnt_h_reg, sc_tclk_cnt_l_reg; 83 #endif /* SINGLE_VRIP_BASE */ 84 int64_t sc_epoch; 85 struct todr_chip_handle sc_todr; 86 struct timecounter sc_tc; 87 }; 88 89 void vrrtc_init(struct device *); 90 int vrrtc_get(todr_chip_handle_t, volatile struct timeval *); 91 int vrrtc_set(todr_chip_handle_t, volatile struct timeval *); 92 uint32_t vrrtc_get_timecount(struct timecounter *); 93 94 struct platform_clock vr_clock = { 95 #define CLOCK_RATE 128 96 CLOCK_RATE, vrrtc_init, 97 }; 98 99 int vrrtc_match(struct device *, struct cfdata *, void *); 100 void vrrtc_attach(struct device *, struct device *, void *); 101 int vrrtc_intr(void*, u_int32_t, u_int32_t); 102 void vrrtc_dump_regs(struct vrrtc_softc *); 103 104 CFATTACH_DECL(vrrtc, sizeof(struct vrrtc_softc), 105 vrrtc_match, vrrtc_attach, NULL, NULL); 106 107 int 108 vrrtc_match(struct device *parent, struct cfdata *cf, void *aux) 109 { 110 111 return (1); 112 } 113 114 #ifndef SINGLE_VRIP_BASE 115 #define RTCINT_REG_W (sc->sc_rtcint_reg) 116 #define TCLK_H_REG_W (sc->sc_tclk_h_reg) 117 #define TCLK_L_REG_W (sc->sc_tclk_l_reg) 118 #define TCLK_CNT_H_REG_W (sc->sc_tclk_cnt_h_reg) 119 #define TCLK_CNT_L_REG_W (sc->sc_tclk_cnt_l_reg) 120 #endif /* SINGLE_VRIP_BASE */ 121 122 void 123 vrrtc_attach(struct device *parent, struct device *self, void *aux) 124 { 125 struct vrip_attach_args *va = aux; 126 struct vrrtc_softc *sc = (void *)self; 127 int year; 128 129 #ifndef SINGLE_VRIP_BASE 130 if (va->va_addr == VR4102_RTC_ADDR) { 131 sc->sc_rtcint_reg = VR4102_RTCINT_REG_W; 132 sc->sc_tclk_h_reg = VR4102_TCLK_H_REG_W; 133 sc->sc_tclk_l_reg = VR4102_TCLK_L_REG_W; 134 sc->sc_tclk_cnt_h_reg = VR4102_TCLK_CNT_H_REG_W; 135 sc->sc_tclk_cnt_l_reg = VR4102_TCLK_CNT_L_REG_W; 136 } else 137 if (va->va_addr == VR4122_RTC_ADDR) { 138 sc->sc_rtcint_reg = VR4122_RTCINT_REG_W; 139 sc->sc_tclk_h_reg = VR4122_TCLK_H_REG_W; 140 sc->sc_tclk_l_reg = VR4122_TCLK_L_REG_W; 141 sc->sc_tclk_cnt_h_reg = VR4122_TCLK_CNT_H_REG_W; 142 sc->sc_tclk_cnt_l_reg = VR4122_TCLK_CNT_L_REG_W; 143 } else 144 if (va->va_addr == VR4181_RTC_ADDR) { 145 sc->sc_rtcint_reg = VR4181_RTCINT_REG_W; 146 sc->sc_tclk_h_reg = RTC_NO_REG_W; 147 sc->sc_tclk_l_reg = RTC_NO_REG_W; 148 sc->sc_tclk_cnt_h_reg = RTC_NO_REG_W; 149 sc->sc_tclk_cnt_l_reg = RTC_NO_REG_W; 150 } else { 151 panic("%s: unknown base address 0x%lx", 152 sc->sc_dev.dv_xname, va->va_addr); 153 } 154 #endif /* SINGLE_VRIP_BASE */ 155 156 sc->sc_iot = va->va_iot; 157 if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 158 0 /* no flags */, &sc->sc_ioh)) { 159 printf("vrrtc_attach: can't map i/o space\n"); 160 return; 161 } 162 /* RTC interrupt handler is directly dispatched from CPU intr */ 163 vr_intr_establish(VR_INTR1, vrrtc_intr, sc); 164 /* But need to set level 1 interrupt mask register, 165 * so regsiter fake interrurpt handler 166 */ 167 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_unit, 0, 168 IPL_CLOCK, 0, 0))) { 169 printf (":can't map interrupt.\n"); 170 return; 171 } 172 /* 173 * Rtc is attached to call this routine 174 * before cpu_initclock() calls clock_init(). 175 * So we must disable all interrupt for now. 176 */ 177 /* 178 * Disable all rtc interrupts 179 */ 180 /* Disable Elapse compare intr */ 181 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ECMP_H_REG_W, 0); 182 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ECMP_M_REG_W, 0); 183 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ECMP_L_REG_W, 0); 184 /* Disable RTC Long1 intr */ 185 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_H_REG_W, 0); 186 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_L_REG_W, 0); 187 /* Disable RTC Long2 intr */ 188 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL2_H_REG_W, 0); 189 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL2_L_REG_W, 0); 190 /* Disable RTC TCLK intr */ 191 if (TCLK_H_REG_W != RTC_NO_REG_W) { 192 bus_space_write_2(sc->sc_iot, sc->sc_ioh, TCLK_H_REG_W, 0); 193 bus_space_write_2(sc->sc_iot, sc->sc_ioh, TCLK_L_REG_W, 0); 194 } 195 /* 196 * Clear all rtc intrrupts. 197 */ 198 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCINT_REG_W, RTCINT_ALL); 199 200 /* 201 * Figure out the epoch, which could be either forward or 202 * backwards in time. We assume that the start date will always 203 * be on Jan 1. 204 */ 205 for (year = EPOCHYEAR; year < POSIX_BASE_YEAR; year++) { 206 sc->sc_epoch += LEAPYEAR4(year) ? SECYR + SECDAY : SECYR; 207 } 208 for (year = POSIX_BASE_YEAR; year < EPOCHYEAR; year++) { 209 sc->sc_epoch -= LEAPYEAR4(year) ? SECYR + SECDAY : SECYR; 210 } 211 212 /* 213 * Initialize MI todr(9) 214 */ 215 sc->sc_todr.todr_settime = vrrtc_set; 216 sc->sc_todr.todr_gettime = vrrtc_get; 217 sc->sc_todr.cookie = sc; 218 todr_attach(&sc->sc_todr); 219 220 platform_clock_attach(sc, &vr_clock); 221 } 222 223 int 224 vrrtc_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 225 { 226 struct vrrtc_softc *sc = arg; 227 struct clockframe cf; 228 229 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCINT_REG_W, RTCINT_ALL); 230 cf.pc = pc; 231 cf.sr = statusReg; 232 hardclock(&cf); 233 234 return 0; 235 } 236 237 void 238 vrrtc_init(struct device *dev) 239 { 240 struct vrrtc_softc *sc = (struct vrrtc_softc *)dev; 241 242 DDUMP_REGS(sc); 243 /* 244 * Set tick (CLOCK_RATE) 245 */ 246 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_H_REG_W, 0); 247 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_L_REG_W, 248 RTCL1_L_HZ/CLOCK_RATE); 249 250 /* 251 * Initialize timecounter. 252 */ 253 sc->sc_tc.tc_get_timecount = vrrtc_get_timecount; 254 sc->sc_tc.tc_name = "vrrtc"; 255 sc->sc_tc.tc_counter_mask = 0xffff; 256 sc->sc_tc.tc_frequency = ETIME_L_HZ; 257 sc->sc_tc.tc_priv = sc; 258 sc->sc_tc.tc_quality = 100; 259 tc_init(&sc->sc_tc); 260 } 261 262 uint32_t 263 vrrtc_get_timecount(struct timecounter *tc) 264 { 265 struct vrrtc_softc *sc = (struct vrrtc_softc *)tc->tc_priv; 266 bus_space_tag_t iot = sc->sc_iot; 267 bus_space_handle_t ioh = sc->sc_ioh; 268 269 return (bus_space_read_2(iot, ioh, ETIME_L_REG_W)); 270 } 271 272 int 273 vrrtc_get(todr_chip_handle_t tch, volatile struct timeval *tvp) 274 { 275 276 struct vrrtc_softc *sc = (struct vrrtc_softc *)tch->cookie; 277 bus_space_tag_t iot = sc->sc_iot; 278 bus_space_handle_t ioh = sc->sc_ioh; 279 u_int32_t timeh; /* elapse time (2*timeh sec) */ 280 u_int32_t timel; /* timel/32768 sec */ 281 int64_t sec, usec; 282 283 timeh = bus_space_read_2(iot, ioh, ETIME_H_REG_W); 284 timeh = (timeh << 16) | bus_space_read_2(iot, ioh, ETIME_M_REG_W); 285 timel = bus_space_read_2(iot, ioh, ETIME_L_REG_W); 286 287 DPRINTF(("clock_get: timeh %08x timel %08x\n", timeh, timel)); 288 289 timeh -= EPOCHOFF; 290 sec = timeh * 2; 291 sec -= sc->sc_epoch; 292 tvp->tv_sec = sec; 293 tvp->tv_sec += timel / ETIME_L_HZ; 294 295 /* scale from 32kHz to 1MHz */ 296 usec = (timel % ETIME_L_HZ); 297 usec *= 1000000; 298 usec /= ETIME_L_HZ; 299 tvp->tv_usec = (uint32_t)usec; 300 301 return 0; 302 } 303 304 int 305 vrrtc_set(todr_chip_handle_t tch, volatile struct timeval *tvp) 306 { 307 struct vrrtc_softc *sc = (struct vrrtc_softc *)tch->cookie; 308 bus_space_tag_t iot = sc->sc_iot; 309 bus_space_handle_t ioh = sc->sc_ioh; 310 u_int32_t timeh; /* elapse time (2*timeh sec) */ 311 u_int32_t timel; /* timel/32768 sec */ 312 int64_t sec, cnt; 313 314 sec = tvp->tv_sec + sc->sc_epoch; 315 sec += sc->sc_epoch; 316 timeh = EPOCHOFF + (sec / 2); 317 timel = sec % 2; 318 319 cnt = tvp->tv_usec; 320 /* scale from 1MHz to 32kHz */ 321 cnt *= ETIME_L_HZ; 322 cnt /= 1000000; 323 timel += (uint32_t)cnt; 324 325 bus_space_write_2(iot, ioh, ETIME_H_REG_W, (timeh >> 16) & 0xffff); 326 bus_space_write_2(iot, ioh, ETIME_M_REG_W, timeh & 0xffff); 327 bus_space_write_2(iot, ioh, ETIME_L_REG_W, timel); 328 329 return 0; 330 } 331 332 void 333 vrrtc_dump_regs(struct vrrtc_softc *sc) 334 { 335 int timeh; 336 int timel; 337 338 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ETIME_H_REG_W); 339 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ETIME_M_REG_W); 340 timel = (timel << 16) 341 | bus_space_read_2(sc->sc_iot, sc->sc_ioh, ETIME_L_REG_W); 342 printf("clock_init() Elapse Time %04x%04x\n", timeh, timel); 343 344 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ECMP_H_REG_W); 345 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ECMP_M_REG_W); 346 timel = (timel << 16) 347 | bus_space_read_2(sc->sc_iot, sc->sc_ioh, ECMP_L_REG_W); 348 printf("clock_init() Elapse Compare %04x%04x\n", timeh, timel); 349 350 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_H_REG_W); 351 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_L_REG_W); 352 printf("clock_init() LONG1 %04x%04x\n", timeh, timel); 353 354 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_CNT_H_REG_W); 355 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_CNT_L_REG_W); 356 printf("clock_init() LONG1 CNTL %04x%04x\n", timeh, timel); 357 358 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_H_REG_W); 359 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_L_REG_W); 360 printf("clock_init() LONG2 %04x%04x\n", timeh, timel); 361 362 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_CNT_H_REG_W); 363 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_CNT_L_REG_W); 364 printf("clock_init() LONG2 CNTL %04x%04x\n", timeh, timel); 365 366 if (TCLK_H_REG_W != RTC_NO_REG_W) { 367 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_H_REG_W); 368 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_L_REG_W); 369 printf("clock_init() TCLK %04x%04x\n", timeh, timel); 370 371 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_CNT_H_REG_W); 372 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_CNT_L_REG_W); 373 printf("clock_init() TCLK CNTL %04x%04x\n", timeh, timel); 374 } 375 } 376