1 /* $NetBSD: icureg.h,v 1.2 1999/12/28 03:15:17 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Shin Takemura. All rights reserved. 5 * Copyright (c) 1999 SATO Kazumi. All rights reserved. 6 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 /* 39 * ICU (Interrupt Control UNIT) Registers definitions 40 * start 0x0B000080 41 */ 42 #define SYSINT1_REG_W 0x000 /* Level1 System intr reg 1 */ 43 #define MSYSINT1_REG_W 0x00c /* Level1 Mask System intr reg 1 */ 44 45 #define SYSINT1_INT15 (1<<15) 46 #define SYSINT1_INT14 (1<<14) 47 #define SYSINT1_DOZEPIU (1<<13) /* PIU intr during Suspend */ 48 #define SYSINT1_INT12 (1<<12) 49 #define SYSINT1_SOFT (1<<11) /* Software intr */ 50 #define SYSINT1_WRBERR (1<<10) /* Bus error intr */ 51 #define SYSINT1_SIU (1<<9) /* SIU intr */ 52 #define SYSINT1_GIU (1<<8) /* GIU intr */ 53 #define SYSINT1_KIU (1<<7) /* KIU intr */ 54 #define SYSINT1_AIU (1<<6) /* AIU intr */ 55 #define SYSINT1_PIU (1<<5) /* PIU intr */ 56 #define SYSINT1_INT4 (1<<4) 57 #define SYSINT1_ETIMER (1<<3) /* ETIMER intr */ 58 #define SYSINT1_RTCL1 (1<<2) /* RTClong1 intr */ 59 #define SYSINT1_POWER (1<<1) /* PowerSW intr */ 60 #define SYSINT1_BAT (1<<0) /* Battery intr */ 61 62 63 #define ICUPIUINT_REG_W 0x002 /* Level2 PIU intr reg */ 64 #define MPIUINT_REG_W 0x00e /* Level2 Mask PIU intr reg */ 65 66 #define PIUINT_PADCMD (1<<6) /* PIU command scan intr */ 67 #define PIUINT_PADADP (1<<5) /* PIU AD port scan intr */ 68 #define PIUINT_PADPAGE1 (1<<4) /* PIU data page 1 intr */ 69 #define PIUINT_PADPAGE0 (1<<3) /* PIU data page 0 intr */ 70 #define PIUINT_PADLOST (1<<2) /* A/D data timeout intr */ 71 #define PIUINT_PENCHG (1) /* Touch Panel contact intr */ 72 73 #define AIUINT_REG_W 0x004 /* Level2 AIU intr reg */ 74 #define MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */ 75 76 #define AIUINT_INTMEND (1<<11) /* Audio input DMA buffer 2 page */ 77 #define AIUINT_INTM (1<<10) /* Audio input DMA buffer 1 page */ 78 #define AIUINT_INTMIDLE (1<<9) /* Audio input idle intr */ 79 #define AIUINT_INTMST (1<<8) /* Audio input receive completion intr */ 80 #define AIUINT_INTSEND (1<<3) /* Audio output buffer 2 page */ 81 #define AIUINT_INTS (1<<2) /* Audio output buffer 1 page */ 82 #define AIUINT_INTSIDLE (1<<1) /* Audio output idle intr */ 83 84 85 #define KIUINT_REG_W 0x006 /* Level2 KIU intr reg */ 86 #define MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */ 87 88 #define KIUINT_KDATLOST (1<<2) /* Key scan data lost */ 89 #define KIUINT_KDATRDY (1<<1) /* Key scan data complete */ 90 #define KIUINT_SCANINT (1) /* Key input detect intr */ 91 92 93 #define GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */ 94 #define MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */ 95 96 #define GIUINT_GPIO15 (1<<15) /* GPIO 15 */ 97 #define GIUINT_GPIO14 (1<<14) /* GPIO 14 */ 98 #define GIUINT_GPIO13 (1<<13) /* GPIO 13 */ 99 #define GIUINT_GPIO12 (1<<12) /* GPIO 12 */ 100 #define GIUINT_GPIO11 (1<<11) /* GPIO 11 */ 101 #define GIUINT_GPIO10 (1<<10) /* GPIO 10 */ 102 #define GIUINT_GPIO9 (1<<9) /* GPIO 9 */ 103 #define GIUINT_GPIO8 (1<<8) /* GPIO 8 */ 104 #define GIUINT_GPIO7 (1<<7) /* GPIO 7 */ 105 #define GIUINT_GPIO6 (1<<6) /* GPIO 6 */ 106 #define GIUINT_GPIO5 (1<<5) /* GPIO 5 */ 107 #define GIUINT_GPIO4 (1<<4) /* GPIO 4 */ 108 #define GIUINT_GPIO3 (1<<3) /* GPIO 3 */ 109 #define GIUINT_GPIO2 (1<<2) /* GPIO 2 */ 110 #define GIUINT_GPIO1 (1<<1) /* GPIO 1 */ 111 #define GIUINT_GPIO0 (1) /* GPIO 0 */ 112 113 114 #define DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */ 115 #define MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */ 116 117 #define DSIUINT_DCTS (1<<11) /* DCTS# change */ 118 #define DSIUINT_SER0 (1<<10) /* Debug serial receive error */ 119 #define DSIUINT_SR0 (1<<9) /* Debug serial receive */ 120 #define DSIUINT_ST0 (1<<8) /* Debug serial transmit */ 121 122 #define NMI_REG_W 0x018 /* NMI reg */ 123 124 #define LOWBATT_NMIORINT (1) /* Low battery type */ 125 #define LOWBATT_INT0 (1) /* Low battery int 0 */ 126 #define LOWBATT_NMI (0) /* Low battery NMI */ 127 128 129 #define SOFTINT_REG_W 0x01a /* Software intr reg */ 130 131 #define SOFTINT_MASK3 (1<<3) /* Softint3 mask */ 132 #define SOFTINT_SET3 (1<<3) /* Softint3 set */ 133 #define SOFTINT_CLEAR3 (0<<3) /* Softint3 clear */ 134 135 #define SOFTINT_MASK2 (1<<2) /* Softint2 mask */ 136 #define SOFTINT_SET2 (1<<2) /* Softint2 set */ 137 #define SOFTINT_CLEAR2 (0<<2) /* Softint2 clear */ 138 139 #define SOFTINT_MASK1 (1<<1) /* Softint1 mask */ 140 #define SOFTINT_SET1 (1<<1) /* Softint1 set */ 141 #define SOFTINT_CLEAR1 (0<<1) /* Softint1 clear */ 142 143 #define SOFTINT_MASK0 (1) /* Softint0 mask */ 144 #define SOFTINT_SET0 (1) /* Softint0 set */ 145 #define SOFTINT_CLEAR0 (0) /* Softint0 clear */ 146 147 148 #define SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */ 149 #define MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */ 150 151 #define SYSINT2_INT31 (1<<15) 152 #define SYSINT2_INT30 (1<<14) 153 #define SYSINT2_INT29 (1<<13) 154 #define SYSINT2_INT28 (1<<12) 155 #define SYSINT2_INT27 (1<<11) 156 #define SYSINT2_INT26 (1<<10) 157 #define SYSINT2_INT25 (1<<9) 158 #define SYSINT2_INT24 (1<<8) 159 #define SYSINT2_INT23 (1<<7) 160 #define SYSINT2_INT22 (1<<6) 161 #define SYSINT2_DSIU (1<<5) /* DSUI intr */ 162 #define SYSINT2_FIR (1<<4) /* FIR intr */ 163 #define SYSINT2_TCLK (1<<3) /* TClock Counter intr */ 164 #define SYSINT2_HSP (1<<2) /* HSP intr */ 165 #define SYSINT2_LED (1<<1) /* LED intr */ 166 #define SYSINT2_RTCL2 (1<<0) /* RTCLong2 intr */ 167 168 169 #define GIUINT_H_REG_W 0x182 /* Level2 GIU intr reg High */ 170 #define MGIUINT_H_REG_W 0x188 /* Level2 Mask GIU intr reg High */ 171 172 #define GIUINT_GPIO31 (1<<15) /* GPIO 31 */ 173 #define GIUINT_GPIO30 (1<<14) /* GPIO 30 */ 174 #define GIUINT_GPIO29 (1<<13) /* GPIO 29 */ 175 #define GIUINT_GPIO28 (1<<12) /* GPIO 28 */ 176 #define GIUINT_GPIO27 (1<<11) /* GPIO 27 */ 177 #define GIUINT_GPIO26 (1<<10) /* GPIO 26 */ 178 #define GIUINT_GPIO25 (1<<9) /* GPIO 25 */ 179 #define GIUINT_GPIO24 (1<<8) /* GPIO 24 */ 180 #define GIUINT_GPIO23 (1<<7) /* GPIO 23 */ 181 #define GIUINT_GPIO22 (1<<6) /* GPIO 22 */ 182 #define GIUINT_GPIO21 (1<<5) /* GPIO 21 */ 183 #define GIUINT_GPIO20 (1<<4) /* GPIO 20 */ 184 #define GIUINT_GPIO19 (1<<3) /* GPIO 19 */ 185 #define GIUINT_GPIO18 (1<<2) /* GPIO 18 */ 186 #define GIUINT_GPIO17 (1<<1) /* GPIO 17 */ 187 #define GIUINT_GPIO16 (1) /* GPIO 16 */ 188 189 190 #define FIRINT_REG_W 0x184 /* Level2 FIR intr reg */ 191 #define MFIRINT_REG_W 0x18a /* Level2 Mask FIR intr reg */ 192 193 #define FIRINT_FIR (1<<4) /* FIR intr */ 194 #define FIRINT_RECV2 (1<<3) /* FIR DMA buf recv buffer2 */ 195 #define FIRINT_TRNS2 (1<<2) /* FIR DMA buf transmit buffer2 */ 196 #define FIRINT_RECV1 (1<<1) /* FIR DMA buf recv buffer1 */ 197 #define FIRINT_TRNS1 (1) /* FIR DMA buf transmit buffer1 */ 198 199 /* END icureg.h */ 200