1 /* $NetBSD: txcsbus.c,v 1.20 2005/12/11 12:17:34 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: txcsbus.c,v 1.20 2005/12/11 12:17:34 christos Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/intr.h> 47 #include <machine/bus.h> 48 #include <machine/bus_space_hpcmips.h> 49 50 #include <machine/platid.h> 51 #include <machine/platid_mask.h> 52 53 #include <hpcmips/tx/tx39var.h> 54 #include <hpcmips/tx/txcsbusvar.h> 55 #include <hpcmips/tx/tx39biuvar.h> 56 #include <hpcmips/tx/tx39biureg.h> 57 58 #include "locators.h" 59 60 /* TX39 CS mapping. (nonconfigurationable) */ 61 const struct csmap { 62 const char *cs_name; 63 paddr_t cs_addr; 64 psize_t cs_size; 65 } __csmap[] = { 66 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 67 TX39_SYSADDR_CS_SIZE}, 68 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 69 TX39_SYSADDR_CS_SIZE}, 70 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 71 TX39_SYSADDR_CS_SIZE}, 72 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 73 TX39_SYSADDR_CS_SIZE}, 74 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 75 TX39_SYSADDR_MCS_SIZE}, 76 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 77 TX39_SYSADDR_MCS_SIZE}, 78 #ifdef TX391X 79 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 80 TX39_SYSADDR_MCS_SIZE}, 81 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 82 TX39_SYSADDR_MCS_SIZE}, 83 #endif /* TX391X */ 84 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 85 TX39_SYSADDR_CARD_SIZE}, 86 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 87 TX39_SYSADDR_CARD_SIZE}, 88 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 89 TX39_SYSADDR_CARD_SIZE}, 90 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 91 TX39_SYSADDR_CARD_SIZE}, 92 [TX39_KUCS0] = {"KUCS0" , TX39_SYSADDR_KUSEG_CS0, 93 TX39_SYSADDR_KUCS_SIZE}, 94 [TX39_KUCS1] = {"KUCS1" , TX39_SYSADDR_KUSEG_CS1, 95 TX39_SYSADDR_KUCS_SIZE}, 96 [TX39_KUCS2] = {"KUCS2" , TX39_SYSADDR_KUSEG_CS2, 97 TX39_SYSADDR_KUCS_SIZE}, 98 [TX39_KUCS3] = {"KUCS3" , TX39_SYSADDR_KUSEG_CS3, 99 TX39_SYSADDR_KUCS_SIZE}, 100 }; 101 102 int txcsbus_match(struct device *, struct cfdata *, void *); 103 void txcsbus_attach(struct device *, struct device *, void *); 104 int txcsbus_print(void *, const char *); 105 int txcsbus_search(struct device *, struct cfdata *, 106 const int *, void *); 107 108 struct txcsbus_softc { 109 struct device sc_dev; 110 tx_chipset_tag_t sc_tc; 111 /* chip select space tag */ 112 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 113 int sc_pri; 114 }; 115 116 CFATTACH_DECL(txcsbus, sizeof(struct txcsbus_softc), 117 txcsbus_match, txcsbus_attach, NULL, NULL); 118 119 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 120 struct cs_handle *); 121 122 int 123 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 124 { 125 struct csbus_attach_args *cba = aux; 126 platid_mask_t mask; 127 128 if (strcmp(cba->cba_busname, cf->cf_name)) 129 return (0); 130 131 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 132 return (1); 133 134 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 135 if (platid_match(&platid, &mask)) 136 return (2); 137 138 return (0); 139 } 140 141 void 142 txcsbus_attach(struct device *parent, struct device *self, void *aux) 143 { 144 struct csbus_attach_args *cba = aux; 145 struct txcsbus_softc *sc = (void*)self; 146 147 sc->sc_tc = cba->cba_tc; 148 printf("\n"); 149 150 /* 151 * Attach external chip. 152 */ 153 /* higher priority devices attach first */ 154 sc->sc_pri = 2; 155 config_search_ia(txcsbus_search, self, "txcsbus", txcsbus_print); 156 /* then, normal priority devices */ 157 sc->sc_pri = 1; 158 config_search_ia(txcsbus_search, self, "txcsbus", txcsbus_print); 159 } 160 161 int 162 txcsbus_print(void *aux, const char *pnp) 163 { 164 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 165 struct cs_attach_args *ca = aux; 166 167 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 168 aprint_normal(" regcs %s %dbit %#x+%#x", 169 __csmap[ca->ca_csreg.cs].cs_name, 170 ca->ca_csreg.cswidth, 171 ca->ca_csreg.csbase, 172 ca->ca_csreg.cssize); 173 } 174 175 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 176 aprint_normal(" iocs %s %dbit %#x+%#x", 177 __csmap[ca->ca_csio.cs].cs_name, 178 ca->ca_csio.cswidth, 179 ca->ca_csio.csbase, 180 ca->ca_csio.cssize); 181 } 182 183 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 184 aprint_normal(" memcs %s %dbit %#x+%#x", 185 __csmap[ca->ca_csmem.cs].cs_name, 186 ca->ca_csmem.cswidth, 187 ca->ca_csmem.csbase, 188 ca->ca_csmem.cssize); 189 } 190 191 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 192 aprint_normal(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 193 } 194 195 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 196 aprint_normal(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 197 } 198 199 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 200 aprint_normal(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 201 } 202 203 return (UNCONF); 204 } 205 206 int 207 txcsbus_search(struct device *parent, struct cfdata *cf, 208 const int *ldesc, void *aux) 209 { 210 struct txcsbus_softc *sc = (void*)parent; 211 struct cs_attach_args ca; 212 213 ca.ca_tc = sc->sc_tc; 214 215 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 216 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 217 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 218 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 219 220 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 221 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 222 } 223 224 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 225 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 226 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 227 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 228 229 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 230 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 231 } 232 233 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 234 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 235 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 236 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 237 238 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 239 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 240 } 241 242 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 243 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 244 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 245 246 if (config_match(parent, cf, &ca) == sc->sc_pri) { 247 config_attach(parent, cf, &ca, txcsbus_print); 248 } 249 250 return (0); 251 } 252 253 bus_space_tag_t 254 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 255 { 256 257 tx_chipset_tag_t tc = sc->sc_tc; 258 int cs = csh->cs; 259 int width = csh->cswidth; 260 struct bus_space_tag_hpcmips *iot; 261 txreg_t reg; 262 263 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs) && 264 !TX39_ISKUCS(cs)) { 265 panic("txcsbus_alloc_tag: bogus chip select %d", cs); 266 } 267 268 /* Already setuped chip select */ 269 if (sc->sc_cst[cs]) { 270 return (&sc->sc_cst[cs]->bst); 271 } 272 273 iot = hpcmips_alloc_bus_space_tag(); 274 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 275 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 276 sc->sc_cst[cs] = iot; 277 278 /* CS bus-width (configurationable) */ 279 switch (width) { 280 default: 281 panic("txcsbus_alloc_tag: bogus bus width %d", width); 282 283 case 32: 284 if (TX39_ISCS(cs)) { 285 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 286 reg |= (1 << cs); 287 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 288 } else if(TX39_ISMCS(cs)) { 289 #ifdef TX391X 290 panic("txcsbus_alloc_tag: MCS is 16bit only"); 291 #endif /* TX391X */ 292 #ifdef TX392X 293 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 294 reg |= ((cs == TX39_MCS0) ? 295 TX39_MEMCONFIG1_MCS0_32 : 296 TX39_MEMCONFIG1_MCS1_32); 297 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 298 #endif /* TX392X */ 299 } 300 break; 301 302 case 16: 303 if (TX39_ISCS(cs)) { 304 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 305 reg &= ~(1 << cs); 306 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 307 } else if(TX39_ISMCS(cs)) { 308 /* TX391X always 16bit port */ 309 #ifdef TX392X 310 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 311 reg &= ~((cs == TX39_MCS0) ? 312 TX39_MEMCONFIG1_MCS0_32 : 313 TX39_MEMCONFIG1_MCS1_32); 314 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 315 #endif /* TX392X */ 316 } else if (TX39_ISCARD(cs)) { 317 /* CARD io/attr or mem */ 318 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 319 320 /* enable I/O access */ 321 reg |= (cs == TX39_CARD1) ? 322 TX39_MEMCONFIG3_CARD1IOEN : 323 TX39_MEMCONFIG3_CARD2IOEN; 324 /* disable 8bit access */ 325 #ifdef TX392X 326 reg &= ~((cs == TX39_CARD1) ? 327 TX39_MEMCONFIG3_CARD1_8SEL : 328 TX39_MEMCONFIG3_CARD2_8SEL); 329 #endif /* TX392X */ 330 #ifdef TX391X 331 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 332 #endif /* TX391X */ 333 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 334 } 335 break; 336 337 case 8: 338 if (TX39_ISCARD(cs)) { 339 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 340 341 /* enable I/O access */ 342 reg |= (cs == TX39_CARD1) ? 343 TX39_MEMCONFIG3_CARD1IOEN : 344 TX39_MEMCONFIG3_CARD2IOEN; 345 /* disable 8bit access */ 346 #ifdef TX392X 347 reg |= (cs == TX39_CARD1) ? 348 TX39_MEMCONFIG3_CARD1_8SEL : 349 TX39_MEMCONFIG3_CARD2_8SEL; 350 #endif /* TX392X */ 351 #ifdef TX391X 352 reg |= TX39_MEMCONFIG3_PORT8SEL; 353 #endif /* TX391X */ 354 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 355 356 } else { 357 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 358 "not allowed", cs); 359 } 360 } 361 362 return (&iot->bst); 363 } 364