1 /* $NetBSD: tx39spireg.h,v 1.1 1999/11/20 19:56:37 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * Toshiba TX3912/3922 SPI module 30 */ 31 32 #define TX39_SPICTRL_REG 0x160 33 #define TX39_SPITXHOLD_REG 0x164 /* W */ 34 #define TX39_SPIRXHOLD_REG 0x164 /* R */ 35 36 /* 37 * SPI Control Register 38 */ 39 /* R */ 40 #define TX39_SPICTRL_SPION 0x00020000 41 #define TX39_SPICTRL_EMPTY 0x00010000 42 /* R/W */ 43 #define TX39_SPICTRL_DELAYVAL_SHIFT 12 44 #define TX39_SPICTRL_DELAYVAL_MASK 0xf 45 #define TX39_SPICTRL_DELAYVAL(cr) \ 46 (((cr) >> TX39_SPICTRL_DELAYVAL_SHIFT) & \ 47 TX39_SPICTRL_DELAYVAL_MASK) 48 #define TX39_SPICTRL_DELAYVAL_SET(cr, val) \ 49 ((cr) | (((val) << TX39_SPICTRL_DELAYVAL_SHIFT) & \ 50 (TX39_SPICTRL_DELAYVAL_MASK << TX39_SPICTRL_DELAYVAL_SHIFT))) 51 /* SPICLK Rate = 7.3728MHz/(BAUDRATE*2 + 2) */ 52 #define TX39_SPICTRL_BAUDRATE_SHIFT 8 53 #define TX39_SPICTRL_BAUDRATE_MASK 0xf 54 #define TX39_SPICTRL_BAUDRATE(cr) \ 55 (((cr) >> TX39_SPICTRL_BAUDRATE_SHIFT) & \ 56 TX39_SPICTRL_BAUDRATE_MASK) 57 #define TX39_SPICTRL_BAUDRATE_SET(cr, val) \ 58 ((cr) | (((val) << TX39_SPICTRL_BAUDRATE_SHIFT) & \ 59 (TX39_SPICTRL_BAUDRATE_MASK << TX39_SPICTRL_BAUDRATE_SHIFT))) 60 #define TX39_SPICTRL_PHAPOL 0x00000020 61 #define TX39_SPICTRL_CLKPOL 0x00000010 62 #define TX39_SPICTRL_WORD 0x00000004 63 #define TX39_SPICTRL_LSB 0x00000002 64 #define TX39_SPICTRL_ENSPI 0x00000001 65 66 /* 67 * SPI Transmitter Holding Register 68 */ 69 /* W */ 70 #define TX39_SPICTRL_TXDATA_SHIFT 0 71 #define TX39_SPICTRL_TXDATA_MASK 0xffff 72 #define TX39_SPICTRL_TXDATA_SET(cr, val) \ 73 ((cr) | (((val) << TX39_SPICTRL_TXDATA_SHIFT) & \ 74 (TX39_SPICTRL_TXDATA_MASK << TX39_SPICTRL_TXDATA_SHIFT))) 75 76 /* 77 * SPI Receiver Holding Register 78 */ 79 /* R */ 80 #define TX39_SPICTRL_RXDATA_SHIFT 8 81 #define TX39_SPICTRL_RXDATA_MASK 0xf 82 #define TX39_SPICTRL_RXDATA(cr) \ 83 (((cr) >> TX39_SPICTRL_RXDATA_SHIFT) & \ 84 TX39_SPICTRL_RXDATA_MASK) 85