1 /* $NetBSD: tx39.c,v 1.20 2000/10/22 10:42:32 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_tx39_debug.h" 40 #include "m38813c.h" 41 #include "tc5165buf.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/kcore.h> 47 48 #include <machine/locore.h> /* cpu_id */ 49 #include <machine/bootinfo.h> /* bootinfo */ 50 #include <machine/sysconf.h> /* platform */ 51 52 #include <machine/platid.h> 53 #include <machine/platid_mask.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <hpcmips/hpcmips/machdep.h> /* cpu_name */ 59 60 #include <hpcmips/tx/tx39biureg.h> 61 #include <hpcmips/tx/tx39reg.h> 62 #include <hpcmips/tx/tx39var.h> 63 #ifdef TX391X 64 #include <hpcmips/tx/tx3912videovar.h> 65 #endif 66 67 #include <sys/termios.h> 68 #include <sys/ttydefaults.h> 69 #include <hpcmips/tx/tx39uartvar.h> 70 #ifndef CONSPEED 71 #define CONSPEED TTYDEF_SPEED 72 #endif 73 74 /* console keyboard */ 75 #if NM38813C > 0 76 #include <hpcmips/dev/m38813cvar.h> 77 #endif 78 #if NTC5165BUF > 0 79 #include <hpcmips/dev/tc5165bufvar.h> 80 #endif 81 82 extern unsigned nullclkread(void); 83 extern unsigned (*clkread)(void); 84 85 struct tx_chipset_tag tx_chipset; 86 87 #ifdef TX39_DEBUG 88 u_int32_t tx39debugflag; 89 #endif 90 91 void tx_init(void); 92 int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 93 void tx39clock_cpuspeed(int*, int*); 94 95 /* TX39-specific initialization vector */ 96 void tx_os_init(void); 97 void tx_bus_reset(void); 98 void tx_cons_init(void); 99 void tx_device_register(struct device *, void *); 100 void tx_fb_init(caddr_t*); 101 void tx_mem_init(paddr_t); 102 void tx_find_dram(paddr_t, paddr_t); 103 void tx_reboot(int, char *); 104 int tx_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 105 106 extern phys_ram_seg_t mem_clusters[]; 107 extern int mem_cluster_cnt; 108 109 void 110 tx_init() 111 { 112 tx_chipset_tag_t tc; 113 int model, rev; 114 int cpuclock; 115 116 tc = tx_conf_get_tag(); 117 /* 118 * Platform Specific Function Hooks 119 */ 120 platform.os_init = tx_os_init; 121 platform.bus_reset = tx_bus_reset; 122 platform.cons_init = tx_cons_init; 123 platform.device_register = tx_device_register; 124 platform.fb_init = tx_fb_init; 125 platform.mem_init = tx_mem_init; 126 platform.reboot = tx_reboot; 127 platform.iointr = tx39icu_intr; 128 129 model = MIPS_PRID_REV(cpu_id); 130 131 switch (model) { 132 default: 133 /* Unknown TOSHIBA TX39-series */ 134 sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x", model); 135 break; 136 case TMPR3912: 137 tx39clock_cpuspeed(&cpuclock, &cpuspeed); 138 139 sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz", 140 cpuclock / 1000000, (cpuclock % 1000000) / 10000); 141 tc->tc_chipset = __TX391X; 142 break; 143 case TMPR3922: 144 tx39clock_cpuspeed(&cpuclock, &cpuspeed); 145 rev = tx_conf_read(tc, TX3922_REVISION_REG); 146 147 sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x " 148 "%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf, 149 cpuclock / 1000000, (cpuclock % 1000000) / 10000); 150 tc->tc_chipset = __TX392X; 151 break; 152 } 153 } 154 155 void 156 tx_os_init() 157 { 158 /* 159 * Set up interrupt handling and I/O addresses. 160 */ 161 162 splvec.splbio = MIPS_SPL_2_4; 163 splvec.splnet = MIPS_SPL_2_4; 164 splvec.spltty = MIPS_SPL_2_4; 165 splvec.splimp = MIPS_SPL_2_4; 166 splvec.splclock = MIPS_SPL_2_4; 167 splvec.splstatclock = MIPS_SPL_2_4; 168 169 /* no high resolution timer circuit; possibly never called */ 170 clkread = nullclkread; 171 } 172 173 void 174 tx_fb_init(kernend) 175 caddr_t *kernend; 176 { 177 #ifdef TX391X 178 paddr_t fb_end; 179 180 fb_end = MIPS_KSEG0_TO_PHYS(mem_clusters[0].start + 181 mem_clusters[0].size - 1); 182 tx3912video_init(MIPS_KSEG0_TO_PHYS(*kernend), &fb_end); 183 184 /* Skip V-RAM area */ 185 *kernend = (caddr_t)MIPS_PHYS_TO_KSEG0(fb_end); 186 #endif /* TX391X */ 187 #ifdef TX392X 188 /* 189 * Plum V-RAM isn't accessible until pmap_bootstrap, 190 * at this time, frame buffer device is disabled. 191 */ 192 bootinfo->fb_addr = 0; 193 #endif /* TX392X */ 194 } 195 196 void 197 tx_mem_init(kernend) 198 paddr_t kernend; 199 { 200 mem_clusters[0].start = 0; 201 mem_clusters[0].size = kernend; 202 mem_cluster_cnt = 1; 203 /* search DRAM bank 0 */ 204 tx_find_dram(kernend, 0x02000000); 205 206 /* search DRAM bank 1 */ 207 tx_find_dram(0x02000000, 0x04000000); 208 /* 209 * Clear currently unused D-RAM area 210 * (For reboot Windows CE clearly) 211 */ 212 memset((void *)(KERNBASE + 0x400), 0, KERNTEXTOFF - 213 (KERNBASE + 0x800)); 214 } 215 216 void 217 tx_find_dram(start, end) 218 paddr_t start, end; 219 { 220 caddr_t page, startaddr, endaddr; 221 222 startaddr = (void*)MIPS_PHYS_TO_KSEG1(start); 223 endaddr = (void*)MIPS_PHYS_TO_KSEG1(end); 224 225 #define DRAM_MAGIC0 0xac1dcafe 226 #define DRAM_MAGIC1 0x19700220 227 228 page = startaddr; 229 if (badaddr(page, 4)) 230 return; 231 232 *(volatile int *)(page + 0) = DRAM_MAGIC0; 233 *(volatile int *)(page + 4) = DRAM_MAGIC1; 234 wbflush(); 235 236 if (*(volatile int *)(page + 0) != DRAM_MAGIC0 || 237 *(volatile int *)(page + 4) != DRAM_MAGIC1) 238 return; 239 240 for (page += NBPG; page < endaddr; page += NBPG) { 241 if (badaddr(page, 4)) 242 return; 243 244 if (*(volatile int *)(page + 0) == DRAM_MAGIC0 && 245 *(volatile int *)(page + 4) == DRAM_MAGIC1) { 246 goto memend_found; 247 } 248 } 249 250 /* check for 32MByte memory */ 251 page -= NBPG; 252 *(volatile int *)(page + 0) = DRAM_MAGIC0; 253 *(volatile int *)(page + 4) = DRAM_MAGIC1; 254 wbflush(); 255 256 if (*(volatile int *)(page + 0) != DRAM_MAGIC0 || 257 *(volatile int *)(page + 4) != DRAM_MAGIC1) 258 return; /* no memory in this bank */ 259 260 memend_found: 261 mem_clusters[mem_cluster_cnt].start = start; 262 mem_clusters[mem_cluster_cnt].size = page - startaddr; 263 264 /* skip kernel area */ 265 if (mem_cluster_cnt == 1) 266 mem_clusters[mem_cluster_cnt].size -= start; 267 268 mem_cluster_cnt++; 269 } 270 271 void 272 tx_reboot(howto, bootstr) 273 int howto; 274 char *bootstr; 275 { 276 goto *(u_int32_t *)MIPS_RESET_EXC_VEC; 277 } 278 279 void 280 tx_bus_reset() 281 { 282 /* hpcmips port don't use */ 283 } 284 285 void 286 tx_cons_init() 287 { 288 int slot; 289 #define CONSPLATIDMATCH(p) \ 290 platid_match(&platid, &platid_mask_MACH_##p) 291 292 #ifdef SERIALCONSSLOT 293 slot = SERIALCONSSLOT; 294 #else 295 slot = TX39_UARTA; 296 #endif 297 if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) { 298 if(txcom_cnattach(slot, CONSPEED, 299 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | 300 CS8)) { 301 panic("tx_cons_init: can't attach serial console."); 302 } 303 } else { 304 #if NM38813C > 0 305 if(CONSPLATIDMATCH(VICTOR_INTERLINK) && 306 m38813c_cnattach(TX39_SYSADDR_CARD1)) { 307 goto panic; 308 } 309 #endif 310 #if NTC5165BUF > 0 311 if(CONSPLATIDMATCH(COMPAQ_C) && 312 tc5165buf_cnattach(TX39_SYSADDR_CS3)) { 313 goto panic; 314 } 315 316 if(CONSPLATIDMATCH(SHARP_TELIOS) && 317 tc5165buf_cnattach(TX39_SYSADDR_CS1)) { 318 goto panic; 319 } 320 321 if(CONSPLATIDMATCH(SHARP_MOBILON) && 322 tc5165buf_cnattach(TX39_SYSADDR_MCS0)) { 323 goto panic; 324 } 325 #endif 326 } 327 328 return; 329 panic: 330 panic("tx_cons_init: can't init console"); 331 /* NOTREACHED */ 332 } 333 334 void 335 tx_device_register(dev, aux) 336 struct device *dev; 337 void *aux; 338 { 339 /* hpcmips port don't use */ 340 } 341 342 void 343 tx_conf_register_intr(t, intrt) 344 tx_chipset_tag_t t; 345 void *intrt; 346 { 347 KASSERT(t == &tx_chipset); 348 349 tx_chipset.tc_intrt = intrt; 350 } 351 352 void 353 tx_conf_register_power(t, powert) 354 tx_chipset_tag_t t; 355 void *powert; 356 { 357 KASSERT(t == &tx_chipset); 358 359 tx_chipset.tc_powert = powert; 360 } 361 362 void 363 tx_conf_register_clock(t, clockt) 364 tx_chipset_tag_t t; 365 void *clockt; 366 { 367 KASSERT(t == &tx_chipset); 368 369 tx_chipset.tc_clockt = clockt; 370 } 371 372 void 373 tx_conf_register_sound(t, soundt) 374 tx_chipset_tag_t t; 375 void *soundt; 376 { 377 KASSERT(t == &tx_chipset); 378 379 tx_chipset.tc_soundt = soundt; 380 } 381 382 void 383 tx_conf_register_ioman(tx_chipset_tag_t t, struct txio_ops *ops) 384 { 385 KASSERT(t == &tx_chipset); 386 KASSERT(ops); 387 388 tx_chipset.tc_ioops[ops->_group] = ops; 389 } 390 391 void 392 tx_conf_register_video(t, videot) 393 tx_chipset_tag_t t; 394 void *videot; 395 { 396 KASSERT(t == &tx_chipset); 397 398 tx_chipset.tc_videot = videot; 399 } 400 401 int 402 __is_set_print(reg, mask, name) 403 u_int32_t reg; 404 int mask; 405 char *name; 406 { 407 const char onoff[2] = "_x"; 408 int ret = reg & mask ? 1 : 0; 409 410 printf("%s[%c] ", name, onoff[ret]); 411 412 return ret; 413 } 414