1 /* $NetBSD: intr.h,v 1.15 2001/09/23 14:32:52 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _HPCMIPS_INTR_H_ 34 #define _HPCMIPS_INTR_H_ 35 36 #include <sys/device.h> 37 #include <sys/lock.h> 38 #include <sys/queue.h> 39 40 #define IPL_NONE 0 /* disable only this interrupt */ 41 42 #define IPL_SOFT 1 /* generic software interrupts (SI 0) */ 43 #define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */ 44 #define IPL_SOFTNET 3 /* network software interrupts (SI 1) */ 45 #define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */ 46 47 #define IPL_BIO 5 /* disable block I/O interrupts */ 48 #define IPL_NET 6 /* disable network interrupts */ 49 #define IPL_TTY 7 /* disable terminal interrupts */ 50 #define IPL_SERIAL 7 /* disable serial hardware interrupts */ 51 #define IPL_CLOCK 8 /* disable clock interrupts */ 52 #define IPL_STATCLOCK 8 /* disable profiling interrupts */ 53 #define IPL_HIGH 8 /* disable all interrupts */ 54 55 #define _IPL_NSOFT 4 56 #define _IPL_N 9 57 58 #define _IPL_SI0_FIRST IPL_SOFT 59 #define _IPL_SI0_LAST IPL_SOFTCLOCK 60 61 #define _IPL_SI1_FIRST IPL_SOFTNET 62 #define _IPL_SI1_LAST IPL_SOFTSERIAL 63 64 #define IPL_SOFTNAMES { \ 65 "misc", \ 66 "clock", \ 67 "net", \ 68 "serial", \ 69 } 70 71 /* Interrupt sharing types. */ 72 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 73 #define IST_NONE 0 /* none */ 74 #define IST_PULSE 1 /* pulsed */ 75 #define IST_EDGE 2 /* edge-triggered */ 76 #define IST_LEVEL 3 /* level-triggered */ 77 78 #ifdef _KERNEL 79 #ifndef _LOCORE 80 #include <mips/cpuregs.h> 81 82 extern const u_int32_t *ipl_sr_bits; 83 extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT]; 84 85 void intr_init(void); 86 int _splraise(int); 87 int _spllower(int); 88 int _splset(int); 89 int _splget(void); 90 void _splnone(void); 91 void _setsoftintr(int); 92 void _clrsoftintr(int); 93 94 #define splhigh() _splraise(ipl_sr_bits[IPL_HIGH]) 95 #define spl0() (void) _spllower(0) 96 #define splx(s) (void) _splset(s) 97 #define splbio() _splraise(ipl_sr_bits[IPL_BIO]) 98 #define splnet() _splraise(ipl_sr_bits[IPL_NET]) 99 #define spltty() _splraise(ipl_sr_bits[IPL_TTY]) 100 #define splserial() _splraise(ipl_sr_bits[IPL_SERIAL]) 101 #define splvm() spltty() 102 #define splclock() _splraise(ipl_sr_bits[IPL_CLOCK]) 103 #define splstatclock() splclock() 104 105 #define splsched() splclock() 106 #define spllock() splhigh() 107 #define spllpt() spltty() 108 109 #define splsoft() _splraise(ipl_sr_bits[IPL_SOFT]) 110 #define splsoftclock() _splraise(ipl_sr_bits[IPL_SOFTCLOCK]) 111 #define splsoftnet() _splraise(ipl_sr_bits[IPL_SOFTNET]) 112 #define splsoftserial() _splraise(ipl_sr_bits[IPL_SOFTSERIAL]) 113 114 #define spllowersoftclock() _spllower(ipl_sr_bits[IPL_SOFTCLOCK]) 115 116 /* 117 * Index into intrcnt[], which is defined in locore 118 */ 119 extern u_long intrcnt[]; 120 121 #define SOFTCLOCK_INTR 0 122 #define SOFTNET_INTR 1 123 #define HARDCLOCK 8 124 125 /* 126 * software simulated interrupt 127 */ 128 #define setsoft(x) \ 129 do { \ 130 _setsoftintr(ipl_si_to_sr[(x) - IPL_SOFT]); \ 131 } while (0) 132 133 struct hpcmips_soft_intrhand { 134 TAILQ_ENTRY(hpcmips_soft_intrhand) 135 sih_q; 136 struct hpcmips_soft_intr *sih_intrhead; 137 void (*sih_fn)(void *); 138 void *sih_arg; 139 int sih_pending; 140 }; 141 142 struct hpcmips_soft_intr { 143 TAILQ_HEAD(, hpcmips_soft_intrhand) 144 softintr_q; 145 struct evcnt softintr_evcnt; 146 struct simplelock softintr_slock; 147 unsigned long softintr_ipl; 148 }; 149 150 void softintr_init(void); 151 void softintr(u_int32_t); 152 void *softintr_establish(int, void (*)(void *), void *); 153 void softintr_disestablish(void *); 154 void softintr_dispatch(void); 155 156 #define softintr_schedule(arg) \ 157 do { \ 158 struct hpcmips_soft_intrhand *__sih = (arg); \ 159 struct hpcmips_soft_intr *__si = __sih->sih_intrhead; \ 160 int __s; \ 161 \ 162 __s = splhigh(); \ 163 simple_lock(&__si->softintr_slock); \ 164 if (__sih->sih_pending == 0) { \ 165 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 166 __sih->sih_pending = 1; \ 167 setsoft(__si->softintr_ipl); \ 168 } \ 169 simple_unlock(&__si->softintr_slock); \ 170 splx(__s); \ 171 } while (0) 172 173 /* XXX For legacy software interrupts. */ 174 extern struct hpcmips_soft_intrhand *softnet_intrhand; 175 176 #define setsoftnet() softintr_schedule(softnet_intrhand) 177 178 #endif /* !_LOCORE */ 179 #endif /* _KERNEL */ 180 181 #endif /* !_HPCMIPS_INTR_H_ */ 182