1 /* $NetBSD: it8368.c,v 1.21 2005/12/24 23:24:00 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: it8368.c,v 1.21 2005/12/24 23:24:00 perry Exp $"); 41 42 #undef WINCE_DEFAULT_SETTING /* for debug */ 43 #undef IT8368DEBUG 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 49 #include <machine/bus.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <hpcmips/tx/tx39var.h> 56 #include <hpcmips/tx/txcsbusvar.h> 57 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 58 #include <hpcmips/dev/it8368var.h> 59 #include <hpcmips/dev/it8368reg.h> 60 61 #ifdef IT8368DEBUG 62 int it8368debug = 1; 63 #define DPRINTF(arg) if (it8368debug) printf arg; 64 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 65 #else 66 #define DPRINTF(arg) 67 #define DPRINTFN(n, arg) 68 #endif 69 70 int it8368e_match(struct device *, struct cfdata *, void *); 71 void it8368e_attach(struct device *, struct device *, void *); 72 int it8368_print(void *, const char *); 73 74 #define IT8368_LASTSTATE_PRESENT 0x0002 75 #define IT8368_LASTSTATE_HALF 0x0001 76 #define IT8368_LASTSTATE_EMPTY 0x0000 77 78 struct it8368e_softc { 79 struct device sc_dev; 80 struct device *sc_pcmcia; 81 tx_chipset_tag_t sc_tc; 82 83 /* Register space */ 84 bus_space_tag_t sc_csregt; 85 bus_space_handle_t sc_csregh; 86 /* I/O, attribute space */ 87 bus_space_tag_t sc_csiot; 88 bus_addr_t sc_csiobase; 89 bus_size_t sc_csiosize; 90 /* 91 * XXX theses means attribute memory. not memory space. 92 * memory space is 0x64000000. 93 */ 94 bus_space_tag_t sc_csmemt; 95 bus_addr_t sc_csmembase; 96 bus_size_t sc_csmemsize; 97 98 /* Separate I/O and attribute space mode */ 99 int sc_fixattr; 100 101 /* Card interrupt handler */ 102 int (*sc_card_fun)(void *); 103 void *sc_card_arg; 104 void *sc_card_ih; 105 int sc_card_irq; 106 107 /* Card status change */ 108 int sc_irq; 109 void *sc_ih; 110 int sc_laststate; 111 }; 112 113 void it8368_init_socket(struct it8368e_softc*); 114 void it8368_attach_socket(struct it8368e_softc *); 115 int it8368_intr(void *); 116 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 117 struct pcmcia_mem_handle *); 118 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 119 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 120 struct pcmcia_mem_handle *, bus_addr_t *, int *); 121 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 122 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 123 bus_size_t, struct pcmcia_io_handle *); 124 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 125 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 126 struct pcmcia_io_handle *, int *); 127 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 128 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 129 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 130 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 131 struct pcmcia_function *, int, int (*) (void *), void *); 132 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 133 134 #ifdef IT8368DEBUG 135 void it8368_dump(struct it8368e_softc *); 136 #endif 137 138 static struct pcmcia_chip_functions it8368_functions = { 139 it8368_chip_mem_alloc, 140 it8368_chip_mem_free, 141 it8368_chip_mem_map, 142 it8368_chip_mem_unmap, 143 it8368_chip_io_alloc, 144 it8368_chip_io_free, 145 it8368_chip_io_map, 146 it8368_chip_io_unmap, 147 it8368_chip_intr_establish, 148 it8368_chip_intr_disestablish, 149 it8368_chip_socket_enable, 150 it8368_chip_socket_disable 151 }; 152 153 CFATTACH_DECL(it8368e, sizeof(struct it8368e_softc), 154 it8368e_match, it8368e_attach, NULL, NULL); 155 156 /* 157 * IT8368 configuration register is big-endian. 158 */ 159 static inline u_int16_t it8368_reg_read(bus_space_tag_t, 160 bus_space_handle_t, int); 161 static inline void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 162 int, u_int16_t); 163 164 #ifdef IT8368E_DESTRUCTIVE_CHECK 165 int it8368e_id_check(void *); 166 167 /* 168 * IT8368E don't have identification method. this is destructive check. 169 */ 170 int 171 it8368e_id_check(void *aux) 172 { 173 struct cs_attach_args *ca = aux; 174 tx_chipset_tag_t tc; 175 bus_space_tag_t csregt; 176 bus_space_handle_t csregh; 177 u_int16_t oreg, reg; 178 int match = 0; 179 180 tc = ca->ca_tc; 181 csregt = ca->ca_csreg.cstag; 182 183 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 184 0, &csregh); 185 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 186 oreg = reg; 187 dbg_bit_print(reg); 188 189 reg &= ~IT8368_CTRL_BYTESWAP; 190 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 191 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 192 if (reg & IT8368_CTRL_BYTESWAP) 193 goto nomatch; 194 195 reg |= IT8368_CTRL_BYTESWAP; 196 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 197 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 198 if (!(reg & IT8368_CTRL_BYTESWAP)) 199 goto nomatch; 200 201 match = 1; 202 nomatch: 203 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 204 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 205 206 return (match); 207 } 208 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 209 210 int 211 it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 #ifdef IT8368E_DESTRUCTIVE_CHECK 214 return (it8368e_id_check(aux)); 215 #else 216 return (1); 217 #endif 218 } 219 220 void 221 it8368e_attach(struct device *parent, struct device *self, void *aux) 222 { 223 struct cs_attach_args *ca = aux; 224 struct it8368e_softc *sc = (void*)self; 225 tx_chipset_tag_t tc; 226 bus_space_tag_t csregt; 227 bus_space_handle_t csregh; 228 u_int16_t reg; 229 230 sc->sc_tc = tc = ca->ca_tc; 231 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 232 233 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 234 0, &sc->sc_csregh); 235 csregh = sc->sc_csregh; 236 sc->sc_csiot = ca->ca_csio.cstag; 237 sc->sc_csiobase = ca->ca_csio.csbase; 238 sc->sc_csiosize = ca->ca_csio.cssize; 239 240 #ifdef IT8368DEBUG 241 printf("\n\t[Windows CE setting]\n"); 242 it8368_dump(sc); /* print WindowsCE setting */ 243 #endif 244 /* LHA[14:13] <= HA[14:13] */ 245 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 246 reg &= ~IT8368_CTRL_ADDRSEL; 247 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 248 249 /* Set all MFIO direction as LHA[23:13] output pins */ 250 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 251 reg |= IT8368_MFIODIR_MASK; 252 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 253 254 /* Set all MFIO functions as LHA */ 255 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 256 reg &= ~IT8368_MFIOSEL_MASK; 257 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 258 259 /* Disable MFIO interrupt */ 260 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 261 reg &= ~IT8368_MFIOPOSINTEN_MASK; 262 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 263 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 264 reg &= ~IT8368_MFIONEGINTEN_MASK; 265 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 266 267 /* Port direction */ 268 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 269 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 270 IT8368_PIN_BCRDRST; 271 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 272 printf("\n"); 273 274 /* 275 * Separate I/O and attribute memory region 276 */ 277 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 278 279 reg |= IT8368_CTRL_FIXATTRIO; 280 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 281 282 if (IT8368_CTRL_FIXATTRIO & 283 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 284 sc->sc_fixattr = 1; 285 printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 286 } else { 287 sc->sc_fixattr = 0; 288 printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 289 } 290 291 sc->sc_csmemt = sc->sc_csiot; 292 sc->sc_csiosize /= 2; 293 sc->sc_csmemsize = sc->sc_csiosize; 294 sc->sc_csmembase = sc->sc_csiosize; 295 296 #ifdef IT8368DEBUG 297 it8368_dump(sc); 298 #endif 299 /* Enable card and interrupt driving. */ 300 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 301 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 302 if (sc->sc_fixattr) 303 reg |= IT8368_CTRL_FIXATTRIO; 304 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 305 306 sc->sc_irq = ca->ca_irq1; 307 sc->sc_card_irq = ca->ca_irq3; 308 309 it8368_attach_socket(sc); 310 } 311 312 inline u_int16_t 313 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 314 { 315 u_int16_t val; 316 317 val = bus_space_read_2(t, h, ofs); 318 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 319 } 320 321 inline void 322 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 323 { 324 u_int16_t val; 325 326 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 327 bus_space_write_2(t, h, ofs, val); 328 } 329 330 int 331 it8368_intr(void *arg) 332 { 333 struct it8368e_softc *sc = arg; 334 bus_space_tag_t csregt = sc->sc_csregt; 335 bus_space_handle_t csregh = sc->sc_csregh; 336 u_int16_t reg; 337 338 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 339 340 if (reg & IT8368_PIN_BCRDRDY) { 341 if (sc->sc_card_fun) { 342 /* clear interrupt */ 343 it8368_reg_write(csregt, csregh, 344 IT8368_GPIONEGINTSTAT_REG, 345 IT8368_PIN_BCRDRDY); 346 347 /* Dispatch card interrupt handler */ 348 (*sc->sc_card_fun)(sc->sc_card_arg); 349 } 350 } else if (reg & IT8368_PIN_CRDDET2) { 351 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 352 IT8368_PIN_CRDDET2); 353 printf("[CSC]\n"); 354 #ifdef IT8368DEBUG 355 it8368_dump(sc); 356 #endif 357 it8368_chip_socket_disable(sc); 358 } else { 359 #ifdef IT8368DEBUG 360 u_int16_t reg2; 361 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 362 printf("unknown it8368 interrupt: "); 363 dbg_bit_print(reg2); 364 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 365 reg); 366 #endif 367 } 368 369 return (0); 370 } 371 372 int 373 it8368_print(void *arg, const char *pnp) 374 { 375 if (pnp) 376 aprint_normal("pcmcia at %s", pnp); 377 378 return (UNCONF); 379 } 380 381 void 382 it8368_attach_socket(struct it8368e_softc *sc) 383 { 384 struct pcmciabus_attach_args paa; 385 386 paa.paa_busname = "pcmcia"; 387 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 388 paa.pch = (pcmcia_chipset_handle_t)sc; 389 paa.iobase = 0; 390 paa.iosize = sc->sc_csiosize; 391 392 if ((sc->sc_pcmcia = config_found_ia((void*)sc, "pcmciabus", &paa, 393 it8368_print))) { 394 it8368_init_socket(sc); 395 } 396 } 397 398 void 399 it8368_init_socket(struct it8368e_softc *sc) 400 { 401 bus_space_tag_t csregt = sc->sc_csregt; 402 bus_space_handle_t csregh = sc->sc_csregh; 403 u_int16_t reg; 404 405 /* 406 * set up the card to interrupt on card detect 407 */ 408 reg = IT8368_PIN_CRDDET2; /* CSC */ 409 /* enable negative edge */ 410 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 411 /* disable positive edge */ 412 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 413 414 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 415 IST_EDGE, IPL_BIO, it8368_intr, sc); 416 if (sc->sc_ih == NULL) { 417 printf("%s: can't establish interrupt\n", 418 sc->sc_dev.dv_xname); 419 return; 420 } 421 422 /* 423 * if there's a card there, then attach it. 424 */ 425 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 426 427 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 428 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 429 } else { 430 pcmcia_card_attach(sc->sc_pcmcia); 431 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 432 } 433 } 434 435 void * 436 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 437 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 438 { 439 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 440 bus_space_tag_t csregt = sc->sc_csregt; 441 bus_space_handle_t csregh = sc->sc_csregh; 442 u_int16_t reg; 443 444 if (sc->sc_card_fun) 445 panic("it8368_chip_intr_establish: " 446 "duplicate card interrupt handler."); 447 448 sc->sc_card_fun = ih_fun; 449 sc->sc_card_arg = ih_arg; 450 451 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 452 IST_EDGE, IPL_BIO, it8368_intr, 453 sc); 454 455 /* enable card interrupt */ 456 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 457 reg |= IT8368_PIN_BCRDRDY; 458 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 459 460 return (sc->sc_card_ih); 461 } 462 463 void 464 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 465 { 466 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 467 bus_space_tag_t csregt = sc->sc_csregt; 468 bus_space_handle_t csregh = sc->sc_csregh; 469 u_int16_t reg; 470 471 if (!sc->sc_card_fun) 472 panic("it8368_chip_intr_disestablish:" 473 "no handler established."); 474 assert(ih == sc->sc_card_ih); 475 476 sc->sc_card_fun = 0; 477 sc->sc_card_arg = 0; 478 479 /* disable card interrupt */ 480 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 481 reg &= ~IT8368_PIN_BCRDRDY; 482 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 483 484 tx_intr_disestablish(sc->sc_tc, ih); 485 } 486 487 int 488 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 489 struct pcmcia_mem_handle *pcmhp) 490 { 491 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 492 493 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 494 sc->sc_csmembase + sc->sc_csmemsize, size, 495 size, 0, 0, 0, &pcmhp->memh)) { 496 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 497 return (1); 498 } 499 500 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 501 pcmhp->memh -= sc->sc_csmembase; 502 503 pcmhp->memt = sc->sc_csmemt; 504 pcmhp->addr = pcmhp->memh; 505 pcmhp->size = size; 506 pcmhp->realsize = size; 507 508 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 509 (unsigned)pcmhp->memh, (unsigned)size)); 510 511 return (0); 512 } 513 514 void 515 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 516 struct pcmcia_mem_handle *pcmhp) 517 { 518 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 519 520 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 521 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 522 523 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 524 pcmhp->memh += sc->sc_csmembase; 525 526 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 527 } 528 529 int 530 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 531 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 532 bus_size_t *offsetp, int *windowp) 533 { 534 /* attribute mode */ 535 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 536 537 *offsetp = card_addr; 538 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 539 (unsigned)pcmhp->memh, (unsigned)size)); 540 541 return (0); 542 } 543 544 void 545 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 546 { 547 /* return to I/O mode */ 548 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 549 } 550 551 void 552 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 553 { 554 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 555 txreg_t reg32; 556 557 DPRINTF(("it8368_mode: change access space to ")); 558 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 559 width == IT8368_WIDTH_8 ? 8 : 16)); 560 561 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 562 563 if (io) { 564 if (width == IT8368_WIDTH_8) 565 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 566 else 567 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 568 } 569 570 if (!sc->sc_fixattr) { 571 if (io) 572 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 573 else 574 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 575 } 576 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 577 578 #ifdef IT8368DEBUG 579 if (sc->sc_fixattr) 580 return; /* No need to report BIU status */ 581 582 /* check BIU status */ 583 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 584 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 585 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 586 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 587 } else { 588 DPRINTF(("it8368_mode: atttribute space enabled\n")); 589 } 590 #endif /* IT8368DEBUG */ 591 } 592 593 int 594 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 595 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 596 { 597 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 598 599 if (start) { 600 if (bus_space_map(sc->sc_csiot, start, size, 0, 601 &pcihp->ioh)) { 602 return (1); 603 } 604 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 605 (unsigned)start, (unsigned)size)); 606 } else { 607 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 608 sc->sc_csiobase + sc->sc_csiosize, 609 size, align, 0, 0, &pcihp->addr, 610 &pcihp->ioh)) { 611 612 return (1); 613 } 614 pcihp->flags = PCMCIA_IO_ALLOCATED; 615 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 616 (unsigned)size, (unsigned)pcihp->addr)); 617 } 618 619 pcihp->iot = sc->sc_csiot; 620 pcihp->size = size; 621 622 return (0); 623 } 624 625 int 626 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 627 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 628 { 629 /* I/O mode */ 630 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 631 632 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 633 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 634 635 return (0); 636 } 637 638 void 639 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 640 struct pcmcia_io_handle *pcihp) 641 { 642 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 643 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 644 else 645 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 646 647 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 648 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 649 } 650 651 void 652 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 653 { 654 655 } 656 657 void 658 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 659 { 660 #ifndef WINCE_DEFAULT_SETTING 661 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 662 bus_space_tag_t csregt = sc->sc_csregt; 663 bus_space_handle_t csregh = sc->sc_csregh; 664 volatile u_int16_t reg; 665 666 /* Power off */ 667 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 668 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 669 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 670 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 671 delay(20000); 672 673 /* 674 * wait 300ms until power fails (Tpf). Then, wait 100ms since 675 * we are changing Vcc (Toff). 676 */ 677 delay((300 + 100) * 1000); 678 679 /* Supply Vcc */ 680 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 681 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 682 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 683 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 684 685 /* 686 * wait 100ms until power raise (Tpr) and 20ms to become 687 * stable (Tsu(Vcc)). 688 * 689 * some machines require some more time to be settled 690 * (300ms is added here). 691 */ 692 delay((100 + 20 + 300) * 1000); 693 694 /* Assert reset signal */ 695 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 696 reg |= IT8368_PIN_BCRDRST; 697 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 698 699 /* 700 * hold RESET at least 10us. 701 */ 702 delay(10); 703 704 /* deassert reset signal */ 705 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 706 reg &= ~IT8368_PIN_BCRDRST; 707 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 708 delay(20000); 709 710 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 711 #endif /* !WINCE_DEFAULT_SETTING */ 712 } 713 714 void 715 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 716 { 717 #ifndef WINCE_DEFAULT_SETTING 718 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 719 bus_space_tag_t csregt = sc->sc_csregt; 720 bus_space_handle_t csregh = sc->sc_csregh; 721 u_int16_t reg; 722 723 /* Power down */ 724 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 725 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 726 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 727 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 728 delay(20000); 729 730 /* 731 * wait 300ms until power fails (Tpf). 732 */ 733 delay(300 * 1000); 734 735 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 736 #endif /* !WINCE_DEFAULT_SETTING */ 737 } 738 739 #ifdef IT8368DEBUG 740 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 741 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT) 742 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 743 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT) 744 void 745 it8368_dump(struct it8368e_softc *sc) 746 { 747 bus_space_tag_t csregt = sc->sc_csregt; 748 bus_space_handle_t csregh = sc->sc_csregh; 749 750 printf("[GPIO]\n"); 751 PRINTGPIO(DIR); 752 PRINTGPIO(DATAIN); 753 PRINTGPIO(DATAOUT); 754 PRINTGPIO(POSINTEN); 755 PRINTGPIO(NEGINTEN); 756 PRINTGPIO(POSINTSTAT); 757 PRINTGPIO(NEGINTSTAT); 758 printf("[MFIO]\n"); 759 PRINTMFIO(SEL); 760 PRINTMFIO(DIR); 761 PRINTMFIO(DATAIN); 762 PRINTMFIO(DATAOUT); 763 PRINTMFIO(POSINTEN); 764 PRINTMFIO(NEGINTEN); 765 PRINTMFIO(POSINTSTAT); 766 PRINTMFIO(NEGINTSTAT); 767 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 768 "CTRL", DBG_BIT_PRINT_COUNT); 769 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 770 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT); 771 } 772 #endif /* IT8368DEBUG */ 773