xref: /netbsd-src/sys/arch/hpcarm/dev/sacc_hpcarm.c (revision 23c8222edbfb0f0932d88a8351d3a0cf817dfb9e)
1 /*      $NetBSD: sacc_hpcarm.c,v 1.1 2003/08/08 12:29:22 bsh Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by IWAMOTO Toshihiro.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Platform dependent part for SA11[01]1 companion chip on hpcarm.
41  */
42 
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: sacc_hpcarm.c,v 1.1 2003/08/08 12:29:22 bsh Exp $");
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/types.h>
49 #include <sys/conf.h>
50 #include <sys/device.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/uio.h>
54 
55 #include <machine/bus.h>
56 #include <machine/platid.h>
57 #include <machine/platid_mask.h>
58 
59 #include <arm/sa11x0/sa11x0_reg.h>
60 #include <arm/sa11x0/sa11x0_var.h>
61 #include <arm/sa11x0/sa11x0_gpioreg.h>
62 #include <arm/sa11x0/sa1111_reg.h>
63 #include <arm/sa11x0/sa1111_var.h>
64 
65 #include "locators.h"
66 
67 static	void	sacc_attach(struct device *, struct device *, void *);
68 static int	sacc_intr(void *);
69 
70 struct platid_data sacc_platid_table[] = {
71 	{ &platid_mask_MACH_HP_JORNADA_720, (void *)1 },
72 	{ &platid_mask_MACH_HP_JORNADA_720JP, (void *)1 },
73 	{ NULL, NULL }
74 };
75 
76 CFATTACH_DECL(sacc, sizeof(struct sacc_softc),
77     sacc_probe, sacc_attach, NULL, NULL);
78 
79 #ifdef INTR_DEBUG
80 #define DPRINTF(arg)	printf arg
81 #else
82 #define DPRINTF(arg)
83 #endif
84 
85 static void
86 sacc_attach(parent, self, aux)
87 	struct device *parent;
88 	struct device *self;
89 	void *aux;
90 {
91 	int i, gpiopin;
92 	u_int32_t skid;
93 	struct sacc_softc *sc = (struct sacc_softc *)self;
94 	struct sa11x0_softc *psc = (struct sa11x0_softc *)parent;
95 	struct sa11x0_attach_args *sa = aux;
96 	struct platid_data *p;
97 
98 	printf("\n");
99 
100 	sc->sc_iot = sa->sa_iot;
101 	sc->sc_piot = psc->sc_iot;
102 	sc->sc_gpioh = psc->sc_gpioh;
103 	if ((p = platid_search_data(&platid, sacc_platid_table)) == NULL)
104 		return;
105 
106 	gpiopin = (int) p->data;
107 	sc->sc_gpiomask = 1 << gpiopin;
108 
109 	if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0,
110 			  &sc->sc_ioh)) {
111 		printf("%s: unable to map registers\n", sc->sc_dev.dv_xname);
112 		return;
113 	}
114 
115 	skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID);
116 
117 	printf("%s: SA1111 rev %d.%d\n", sc->sc_dev.dv_xname,
118 	       (skid & 0xf0) >> 3, skid & 0xf);
119 
120 	for(i = 0; i < SACCIC_LEN; i++)
121 		sc->sc_intrhand[i] = NULL;
122 
123 	/* initialize SA1111 interrupt controller */
124 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0);
125 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0);
126 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0);
127 	bus_space_write_4(sc->sc_iot, sc->sc_ioh,
128 			  SACCIC_INTSTATCLR0, 0xffffffff);
129 	bus_space_write_4(sc->sc_iot, sc->sc_ioh,
130 			  SACCIC_INTSTATCLR1, 0xffffffff);
131 
132 	/* connect to SA1110's GPIO intr */
133 	sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc);
134 
135 	/*
136 	 *  Attach each devices
137 	 */
138 	config_search(sa1111_search, self, NULL);
139 }
140 
141 static int
142 sacc_intr(arg)
143 	void *arg;
144 {
145 	int i;
146 	u_int32_t mask;
147 	struct sacc_intrvec intstat;
148 	struct sacc_softc *sc = arg;
149 	struct sacc_intrhand *ih;
150 
151 	intstat.lo =
152 	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0);
153 	intstat.hi =
154 	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1);
155 	DPRINTF(("sacc_intr_dispatch: %x %x\n", intstat.lo, intstat.hi));
156 
157 	/* clear SA1110's GPIO intr status */
158 	bus_space_write_4(sc->sc_piot, sc->sc_gpioh,
159 			  SAGPIO_EDR, sc->sc_gpiomask);
160 
161 	for(i = 0, mask = 1; i < 32; i++, mask <<= 1)
162 		if (intstat.lo & mask) {
163 			/*
164 			 * Clear intr status before calling intr handlers.
165 			 * This cause stray interrupts, but clearing
166 			 * after calling intr handlers cause intr lossage.
167 			 */
168 			bus_space_write_4(sc->sc_iot, sc->sc_ioh,
169 					  SACCIC_INTSTATCLR0, 1 << i);
170 
171 			for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next)
172 				softintr_schedule(ih->ih_soft);
173 		}
174 	for(i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1)
175 		if (intstat.hi & mask) {
176 			bus_space_write_4(sc->sc_iot, sc->sc_ioh,
177 					  SACCIC_INTSTATCLR1, 1 << i);
178 			for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next)
179 				softintr_schedule(ih->ih_soft);
180 		}
181 	return 1;
182 }
183