1 /* $NetBSD: sh_arch.cpp,v 1.11 2004/08/13 15:50:09 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <hpcboot.h> 40 #include <hpcmenu.h> 41 #include <sh3/sh_arch.h> 42 43 SH_BOOT_FUNC_(7707); 44 SH_BOOT_FUNC_(7709); 45 SH_BOOT_FUNC_(7709A); 46 SH_BOOT_FUNC_(7750); 47 48 static int _cpu_type; 49 50 int 51 SHArchitecture::cpu_type() 52 { 53 if (_cpu_type == 0) { 54 #if _WIN32_WCE == 101 55 _cpu_type = 3; 56 #else 57 SYSTEM_INFO si; 58 GetSystemInfo(&si); 59 _cpu_type = si.wProcessorLevel; 60 #endif 61 } 62 63 return _cpu_type; 64 } 65 66 BOOL 67 SHArchitecture::init() 68 { 69 70 if (!_mem->init()) { 71 DPRINTF((TEXT("can't initialize memory manager.\n"))); 72 return FALSE; 73 } 74 // D-RAM information 75 DPRINTF((TEXT("Memory Bank:\n"))); 76 77 return TRUE; 78 } 79 80 void 81 SHArchitecture::systemInfo() 82 { 83 84 // Windows CE common infomation. 85 super::systemInfo(); 86 87 // CPU specific. 88 _dev->dump(HPC_MENU._cons_parameter); 89 } 90 91 BOOL 92 SHArchitecture::setupLoader() 93 { 94 vaddr_t v; 95 96 if (!_mem->getPage(v , _loader_addr)) { 97 DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 98 return FALSE; 99 } 100 _loader_addr = ptokv(_loader_addr); 101 102 DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"), 103 (unsigned)v,(unsigned)_loader_addr)); 104 105 memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 106 107 return TRUE; 108 } 109 110 void 111 SHArchitecture::jump(paddr_t info, paddr_t pvec) 112 { 113 kaddr_t sp; 114 vaddr_t v; 115 paddr_t p; 116 117 // stack for bootloader 118 _mem->getPage(v, p); 119 sp = ptokv(p + _mem->getPageSize() / 2); 120 121 info = ptokv(info); 122 pvec = ptokv(pvec); 123 124 DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"), 125 info, sp)); 126 127 // Change to privilege-mode. 128 SetKMode(1); 129 130 // Cache flush(for 2nd bootloader) 131 // 132 // SH4 uses WinCE CacheSync(). this routine may causes TLB 133 // exception. so calls before suspendIntr(). 134 // 135 cache_flush(); 136 137 // Disable external interrupt. 138 suspendIntr(); 139 140 // jump to 2nd loader.(run P1) at this time I still use MMU. 141 __asm( 142 "mov r6, r15\n" 143 "jmp @r7\n" 144 "nop \n", info, pvec, sp, _loader_addr); 145 // NOTREACHED 146 } 147 148 // disable external interrupt and save its priority. 149 u_int32_t 150 suspendIntr() 151 { 152 u_int32_t sr; 153 154 __asm( 155 "stc sr, r0\n" 156 "mov.l r0, @r4\n" 157 "or r5, r0\n" 158 "ldc r0, sr\n", &sr, 0x000000f0); 159 return sr & 0x000000f0; 160 } 161 162 // resume external interrupt priority. 163 void 164 resumeIntr(u_int32_t s) 165 { 166 167 __asm( 168 "stc sr, r0\n" 169 "and r5, r0\n" 170 "or r4, r0\n" 171 "ldc r0, sr\n", s, 0xffffff0f); 172 } 173