1 /* $NetBSD: cpu.h,v 1.9 1994/10/26 07:26:19 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 /* 46 * Exported definitions unique to hp300/68k cpu support. 47 */ 48 49 /* 50 * definitions of cpu-dependent requirements 51 * referenced in generic code 52 */ 53 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 54 55 #define cpu_exec(p) /* nothing */ 56 #define cpu_swapin(p) /* nothing */ 57 #define cpu_wait(p) /* nothing */ 58 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 59 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 60 61 /* 62 * Arguments to hardclock and gatherstats encapsulate the previous 63 * machine state in an opaque clockframe. One the hp300, we use 64 * what the hardware pushes on an interrupt (frame format 0). 65 */ 66 struct clockframe { 67 u_short sr; /* sr at time of interrupt */ 68 u_long pc; /* pc at time of interrupt */ 69 u_short vo; /* vector offset (4-word frame) */ 70 }; 71 72 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 73 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 74 #define CLKF_PC(framep) ((framep)->pc) 75 #if 0 76 /* We would like to do it this way... */ 77 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 78 #else 79 /* but until we start using PSL_M, we have to do this instead */ 80 #define CLKF_INTR(framep) (0) /* XXX */ 81 #endif 82 83 84 /* 85 * Preempt the current process if in interrupt from user mode, 86 * or after the current trap/syscall if in system mode. 87 */ 88 #define need_resched() { want_resched++; aston(); } 89 90 /* 91 * Give a profiling tick to the current process when the user profiling 92 * buffer pages are invalid. On the hp300, request an ast to send us 93 * through trap, marking the proc as needing a profiling tick. 94 */ 95 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 96 97 /* 98 * Notify the current process (p) that it has a signal pending, 99 * process as soon as possible. 100 */ 101 #define signotify(p) aston() 102 103 #define aston() (astpending++) 104 105 int astpending; /* need to trap before returning to user mode */ 106 int want_resched; /* resched() was called */ 107 108 109 /* 110 * simulated software interrupt register 111 */ 112 extern unsigned char ssir; 113 114 #define SIR_NET 0x1 115 #define SIR_CLOCK 0x2 116 117 #define siroff(x) ssir &= ~(x) 118 #define setsoftnet() ssir |= SIR_NET 119 #define setsoftclock() ssir |= SIR_CLOCK 120 121 /* 122 * CTL_MACHDEP definitions. 123 */ 124 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 125 #define CPU_MAXID 2 /* number of valid machdep ids */ 126 127 #define CTL_MACHDEP_NAMES { \ 128 { 0, 0 }, \ 129 { "console_device", CTLTYPE_STRUCT }, \ 130 } 131 132 /* 133 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 134 * although some of it could probably be put into generic 68k headers. 135 */ 136 137 /* values for machineid */ 138 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 139 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 140 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 141 #define HP_360 3 /* 25Mhz 68030 */ 142 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 143 #define HP_340 5 /* 16Mhz 68030 */ 144 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 145 #define HP_380 7 /* 25Mhz 68040 */ 146 #define HP_433 8 /* 33Mhz 68040 */ 147 148 /* values for mmutype (assigned for quick testing) */ 149 #define MMU_68040 -2 /* 68040 on-chip MMU */ 150 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 151 #define MMU_HP 0 /* HP proprietary */ 152 #define MMU_68851 1 /* Motorola 68851 */ 153 154 /* values for ectype */ 155 #define EC_PHYS -1 /* external physical address cache */ 156 #define EC_NONE 0 /* no external cache */ 157 #define EC_VIRT 1 /* external virtual address cache */ 158 159 /* values for cpuspeed (not really related to clock speed due to caches) */ 160 #define MHZ_8 1 161 #define MHZ_16 2 162 #define MHZ_25 3 163 #define MHZ_33 4 164 #define MHZ_50 6 165 166 #ifdef KERNEL 167 extern int machineid, mmutype, ectype; 168 extern char *intiobase, *intiolimit; 169 170 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 171 #define enablertclock() 172 173 #endif 174 175 /* physical memory sections */ 176 #define ROMBASE (0x00000000) 177 #define INTIOBASE (0x00400000) 178 #define INTIOTOP (0x00600000) 179 #define EXTIOBASE (0x00600000) 180 #define EXTIOTOP (0x20000000) 181 #define MAXADDR (0xFFFFF000) 182 183 /* 184 * Internal IO space: 185 * 186 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 187 * 188 * Internal IO space is mapped in the kernel from ``intiobase'' to 189 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 190 * conversion between physical and kernel virtual addresses is easy. 191 */ 192 #define ISIIOVA(va) \ 193 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 194 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 195 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 196 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 197 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 198 199 /* 200 * External IO space: 201 * 202 * DIO ranges from select codes 0-63 at physical addresses given by: 203 * 0x600000 + (sc - 32) * 0x10000 204 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for 205 * their control space and the remaining areas, [0x200000-0x400000) and 206 * [0x800000-0x1000000), are for additional space required by a card; 207 * e.g. a display framebuffer. 208 * 209 * DIO-II ranges from select codes 132-255 at physical addresses given by: 210 * 0x1000000 + (sc - 132) * 0x400000 211 * The address range of DIO-II space is thus [0x1000000-0x20000000). 212 * 213 * DIO/DIO-II space is too large to map in its entirety, instead devices 214 * are mapped into kernel virtual address space allocated from a range 215 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. 216 */ 217 #define DIOBASE (0x600000) 218 #define DIOTOP (0x1000000) 219 #define DIOCSIZE (0x10000) 220 #define DIOIIBASE (0x01000000) 221 #define DIOIITOP (0x20000000) 222 #define DIOIICSIZE (0x00400000) 223 224 /* 225 * HP MMU 226 */ 227 #define MMUBASE IIOPOFF(0x5F4000) 228 #define MMUSSTP 0x0 229 #define MMUUSTP 0x4 230 #define MMUTBINVAL 0x8 231 #define MMUSTAT 0xC 232 #define MMUCMD MMUSTAT 233 234 #define MMU_UMEN 0x0001 /* enable user mapping */ 235 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 236 #define MMU_CEN 0x0004 /* enable data cache */ 237 #define MMU_BERR 0x0008 /* bus error */ 238 #define MMU_IEN 0x0020 /* enable instruction cache */ 239 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 240 #define MMU_WPF 0x2000 /* write protect fault */ 241 #define MMU_PF 0x4000 /* page fault */ 242 #define MMU_PTF 0x8000 /* page table fault */ 243 244 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 245 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 246 247 /* 248 * 68851 and 68030 MMU 249 */ 250 #define PMMU_LVLMASK 0x0007 251 #define PMMU_INV 0x0400 252 #define PMMU_WP 0x0800 253 #define PMMU_ALV 0x1000 254 #define PMMU_SO 0x2000 255 #define PMMU_LV 0x4000 256 #define PMMU_BE 0x8000 257 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 258 259 /* 260 * 68040 MMU 261 */ 262 #define MMU4_RES 0x001 263 #define MMU4_TTR 0x002 264 #define MMU4_WP 0x004 265 #define MMU4_MOD 0x010 266 #define MMU4_CMMASK 0x060 267 #define MMU4_SUP 0x080 268 #define MMU4_U0 0x100 269 #define MMU4_U1 0x200 270 #define MMU4_GLB 0x400 271 #define MMU4_BE 0x800 272 273 /* 680X0 function codes */ 274 #define FC_USERD 1 /* user data space */ 275 #define FC_USERP 2 /* user program space */ 276 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 277 #define FC_SUPERD 5 /* supervisor data space */ 278 #define FC_SUPERP 6 /* supervisor program space */ 279 #define FC_CPU 7 /* CPU space */ 280 281 /* fields in the 68020 cache control register */ 282 #define IC_ENABLE 0x0001 /* enable instruction cache */ 283 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 284 #define IC_CE 0x0004 /* clear instruction cache entry */ 285 #define IC_CLR 0x0008 /* clear entire instruction cache */ 286 287 /* additional fields in the 68030 cache control register */ 288 #define IC_BE 0x0010 /* instruction burst enable */ 289 #define DC_ENABLE 0x0100 /* data cache enable */ 290 #define DC_FREEZE 0x0200 /* data cache freeze */ 291 #define DC_CE 0x0400 /* clear data cache entry */ 292 #define DC_CLR 0x0800 /* clear entire data cache */ 293 #define DC_BE 0x1000 /* data burst enable */ 294 #define DC_WA 0x2000 /* write allocate */ 295 296 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 297 #define CACHE_OFF (DC_CLR|IC_CLR) 298 #define CACHE_CLR (CACHE_ON) 299 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 300 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 301 302 /* 68040 cache control register */ 303 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 304 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 305 306 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 307 #define CACHE4_OFF (0) 308