xref: /netbsd-src/sys/arch/hp300/dev/spc.c (revision 23c8222edbfb0f0932d88a8351d3a0cf817dfb9e)
1 /* $NetBSD: spc.c,v 1.3 2004/08/28 17:37:02 thorpej Exp $ */
2 
3 /*
4  * Copyright (c) 2003 Izumi Tsutsui.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  *    derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #include "opt_ddb.h"
31 
32 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
33 
34 __KERNEL_RCSID(0, "$NetBSD: spc.c,v 1.3 2004/08/28 17:37:02 thorpej Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/device.h>
39 
40 #include <machine/autoconf.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/intr.h>
44 
45 #include <hp300/dev/dioreg.h>
46 #include <hp300/dev/diovar.h>
47 #include <hp300/dev/diodevs.h>
48 
49 #include <dev/scsipi/scsi_all.h>
50 #include <dev/scsipi/scsipi_all.h>
51 #include <dev/scsipi/scsi_message.h>
52 #include <dev/scsipi/scsiconf.h>
53 
54 #include <dev/ic/mb89352reg.h>
55 #include <dev/ic/mb89352var.h>
56 
57 #include <hp300/dev/hp98265reg.h>
58 #include <hp300/dev/dmareg.h>
59 #include <hp300/dev/dmavar.h>
60 
61 static int	spc_dio_match(struct device *, struct cfdata *, void *);
62 static void	spc_dio_attach(struct device *, struct device *, void *);
63 static void	spc_dio_dmastart(struct spc_softc *, void *, size_t, int);
64 static void	spc_dio_dmadone(struct spc_softc *);
65 static void	spc_dio_dmago(void *);
66 static void	spc_dio_dmastop(void *);
67 
68 struct spc_dio_softc {
69 	struct spc_softc sc_spc;	/* MI spc softc */
70 
71 	/* DIO specific goo. */
72 	struct bus_space_tag sc_tag;	/* bus space tag with oddbyte func */
73 	bus_space_handle_t sc_iohsc;	/* bus space handle for HPSCSI */
74 	struct dmaqueue sc_dq;		/* DMA job queue */
75 	u_int sc_dflags;		/* DMA flags */
76 #define SCSI_DMA32	0x01		/* 32-bit DMA should be used */
77 #define SCSI_HAVEDMA	0x02		/* controller has DMA channel */
78 #define SCSI_DATAIN	0x04		/* DMA direction */
79 };
80 
81 CFATTACH_DECL(spc, sizeof(struct spc_dio_softc),
82     spc_dio_match, spc_dio_attach, NULL, NULL);
83 
84 static int
85 spc_dio_match(struct device *parent, struct cfdata *cf, void *aux)
86 {
87 	struct dio_attach_args *da = aux;
88 
89 	switch (da->da_id) {
90 	case DIO_DEVICE_ID_SCSI0:
91 	case DIO_DEVICE_ID_SCSI1:
92 	case DIO_DEVICE_ID_SCSI2:
93 	case DIO_DEVICE_ID_SCSI3:
94 		return 1;
95 	}
96 
97 	return 0;
98 }
99 
100 static void
101 spc_dio_attach(struct device *parent, struct device *self, void *aux)
102 {
103 	struct spc_dio_softc *dsc = (struct spc_dio_softc *)self;
104 	struct spc_softc *sc = &dsc->sc_spc;
105 	struct dio_attach_args *da = aux;
106 	bus_space_tag_t iot = &dsc->sc_tag;
107 	bus_space_handle_t iohsc, iohspc;
108 	u_int8_t id;
109 
110 	memcpy(iot, da->da_bst, sizeof(struct bus_space_tag));
111 	dio_set_bus_space_oddbyte(iot);
112 
113 	if (bus_space_map(iot, da->da_addr, da->da_size, 0, &iohsc)) {
114 		printf(": can't map SCSI registers\n");
115 		return;
116 	}
117 
118 	if (bus_space_subregion(iot, iohsc, SPC_OFFSET, SPC_SIZE, &iohspc)) {
119 		printf(": can't map SPC registers\n");
120 		return;
121 	}
122 
123 	printf(": 98265A SCSI");
124 
125 	bus_space_write_1(iot, iohsc, HPSCSI_ID, 0xff);
126 	DELAY(100);
127 	id = bus_space_read_1(iot, iohsc, HPSCSI_ID);
128 	if ((id & ID_WORD_DMA) == 0) {
129 		printf(", 32-bit DMA");
130 		dsc->sc_dflags |= SCSI_DMA32;
131 	}
132 	id &= ID_MASK;
133 	printf(", SCSI ID %d\n", id);
134 
135 	sc->sc_iot = iot;
136 	sc->sc_ioh = iohspc;
137 	sc->sc_initiator = id;
138 
139 	sc->sc_dma_start = spc_dio_dmastart;
140 	sc->sc_dma_done  = spc_dio_dmadone;
141 
142 	dsc->sc_iohsc = iohsc;
143 	dsc->sc_dq.dq_softc = dsc;
144 	dsc->sc_dq.dq_start = spc_dio_dmago;
145 	dsc->sc_dq.dq_done  = spc_dio_dmastop;
146 
147 	bus_space_write_1(iot, iohsc, HPSCSI_CSR, 0x00);
148 	bus_space_write_1(iot, iohsc, HPSCSI_HCONF, 0x00);
149 
150 	dio_intr_establish(spc_intr, (void *)sc, da->da_ipl, IPL_BIO);
151 
152 	spc_attach(sc);
153 
154 	/* Enable SPC interrupts. */
155 	bus_space_write_1(iot, iohsc, HPSCSI_CSR, CSR_IE);
156 }
157 
158 static void
159 spc_dio_dmastart(struct spc_softc *sc, void *addr, size_t size, int datain)
160 {
161 	struct spc_dio_softc *dsc = (struct spc_dio_softc *)sc;
162 
163 	dsc->sc_dq.dq_chan = DMA0 | DMA1;
164 	dsc->sc_dflags |= SCSI_HAVEDMA;
165 	if (datain)
166 		dsc->sc_dflags |= SCSI_DATAIN;
167 	else
168 		dsc->sc_dflags &= ~SCSI_DATAIN;
169 
170 	if (dmareq(&dsc->sc_dq) != 0)
171 		/* DMA channel is available, so start DMA immediately */
172 		spc_dio_dmago((void *)dsc);
173 	/* else dma start function will be called later from dmafree(). */
174 }
175 
176 static void
177 spc_dio_dmago(void *arg)
178 {
179 	struct spc_dio_softc *dsc = (struct spc_dio_softc *)arg;
180 	struct spc_softc *sc = &dsc->sc_spc;
181 	bus_space_tag_t iot;
182 	bus_space_handle_t iohsc, iohspc;
183 	int len, chan;
184 	u_int32_t dmaflags;
185 	u_int8_t cmd;
186 
187 	iot = sc->sc_iot;
188 	iohspc = sc->sc_ioh;
189 	iohsc = dsc->sc_iohsc;
190 
191 	bus_space_write_1(iot, iohsc, HPSCSI_HCONF, 0);
192 
193 	cmd = CSR_IE;
194 	dmaflags = DMAGO_NOINT;
195 	chan = dsc->sc_dq.dq_chan;
196 	if ((dsc->sc_dflags & SCSI_DATAIN) != 0) {
197 		cmd |= CSR_DMAIN;
198 		dmaflags |= DMAGO_READ;
199 	}
200 	if ((dsc->sc_dflags & SCSI_DMA32) != 0 &&
201 	    ((u_int)sc->sc_dp & 3) == 0 &&
202 	    (sc->sc_dleft & 3) == 0) {
203 		cmd |= CSR_DMA32;
204 		dmaflags |= DMAGO_LWORD;
205 	} else
206 		dmaflags |= DMAGO_WORD;
207 
208 	dmago(chan, sc->sc_dp, sc->sc_dleft, dmaflags);
209 
210 	bus_space_write_1(iot, iohsc, HPSCSI_CSR, cmd);
211 	cmd |= (chan == 0) ? CSR_DE0 : CSR_DE1;
212 	bus_space_write_1(iot, iohsc, HPSCSI_CSR, cmd);
213 
214 	cmd = SCMD_XFR;
215 	len = sc->sc_dleft;
216 
217 	if ((len & (DEV_BSIZE - 1)) != 0) /* XXX ??? */ {
218 		cmd |= SCMD_PAD;
219 #if 0
220 		if ((dsc->sc_dflags & SCSI_DATAIN) != 0)
221 			len += 2; /* XXX ??? */
222 #endif
223 	}
224 
225 	bus_space_write_1(iot, iohspc, TCH, len >> 16);
226 	bus_space_write_1(iot, iohspc, TCM, len >>  8);
227 	bus_space_write_1(iot, iohspc, TCL, len);
228 	bus_space_write_1(iot, iohspc, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
229 	bus_space_write_1(iot, iohspc, SCMD, cmd);
230 
231 	sc->sc_flags |= SPC_DOINGDMA;
232 }
233 
234 static void
235 spc_dio_dmadone(struct spc_softc *sc)
236 {
237 	struct spc_dio_softc *dsc = (struct spc_dio_softc *)sc;
238 	bus_space_tag_t iot;
239 	bus_space_handle_t ioh, iohsc;
240 	int resid, trans;
241 	u_int8_t cmd;
242 
243 	iot = sc->sc_iot;
244 	ioh = sc->sc_ioh;
245 	iohsc = dsc->sc_iohsc;
246 
247 	/* wait DMA complete */
248 	if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) {
249 		int timeout = 1000; /* XXX how long? */
250 		while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) {
251 			if (--timeout < 0)
252 				printf("%s: DMA complete timeout\n",
253 				    sc->sc_dev.dv_xname);
254 			DELAY(1);
255 		}
256 	}
257 
258 	if ((dsc->sc_dflags & SCSI_HAVEDMA) != 0) {
259 		dmafree(&dsc->sc_dq);
260 		dsc->sc_dflags &= ~SCSI_HAVEDMA;
261 	}
262 
263 	cmd = bus_space_read_1(iot, iohsc, HPSCSI_CSR);
264 	cmd &= ~(CSR_DE1|CSR_DE0);
265 	bus_space_write_1(iot, iohsc, HPSCSI_CSR, cmd);
266 
267 	resid = bus_space_read_1(iot, ioh, TCH) << 16 |
268 	    bus_space_read_1(iot, ioh, TCM) << 8 |
269 	    bus_space_read_1(iot, ioh, TCL);
270 	trans = sc->sc_dleft - resid;
271 	sc->sc_dp += trans;
272 	sc->sc_dleft -= trans;
273 
274 	sc->sc_flags &= ~SPC_DOINGDMA;
275 }
276 
277 static void
278 spc_dio_dmastop(void *arg)
279 {
280 	struct spc_dio_softc *dsc = (struct spc_dio_softc *)arg;
281 	struct spc_softc *sc = &dsc->sc_spc;
282 	u_int8_t cmd;
283 
284 	/* XXX When is this function called? */
285 	cmd = bus_space_read_1(sc->sc_iot, dsc->sc_iohsc, HPSCSI_CSR);
286 	cmd &= ~(CSR_DE1|CSR_DE0);
287 	bus_space_write_1(sc->sc_iot, dsc->sc_iohsc, HPSCSI_CSR, cmd);
288 
289 	dsc->sc_dflags &= ~SCSI_HAVEDMA;
290 	sc->sc_flags &= ~SPC_DOINGDMA;
291 }
292