1 /* $NetBSD: dmareg.h,v 1.4 1994/10/26 07:23:41 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)dmareg.h 8.1 (Berkeley) 6/10/93 36 */ 37 38 #include <hp300/dev/iotypes.h> /* XXX */ 39 40 /* 41 * Hardware layout for the 98620[ABC]: 42 * 98620A (old 320s?): byte/word DMA in up to 64K chunks 43 * 98620B (320s only): 98620A with programmable IPL 44 * 98620C (all others): byte/word/longword DMA in up to 4Gb chunks 45 */ 46 47 struct dmaBdevice { 48 v_char *dmaB_addr; 49 vu_short dmaB_count; 50 vu_short dmaB_cmd; 51 #define dmaB_stat dmaB_cmd 52 }; 53 54 struct dmadevice { 55 v_char *dma_addr; 56 vu_int dma_count; 57 vu_short dma_cmd; 58 vu_short dma_stat; 59 }; 60 61 struct dmareg { 62 struct dmaBdevice dma_Bchan0; 63 struct dmaBdevice dma_Bchan1; 64 /* the rest are 98620C specific */ 65 v_char dma_id[4]; 66 vu_char dma_cr; 67 char dma_pad1[0xEB]; 68 struct dmadevice dma_chan0; 69 char dma_pad2[0xF4]; 70 struct dmadevice dma_chan1; 71 }; 72 73 #define NDMA 2 74 75 /* intr level must be >= level of any device using dma. i.e., splbio */ 76 #define DMAINTLVL 5 77 78 /* addresses */ 79 #define DMA_BASE IIOV(0x500000) 80 81 /* command bits */ 82 #define DMA_ENAB 0x0001 83 #define DMA_WORD 0x0002 84 #define DMA_WRT 0x0004 85 #define DMA_PRI 0x0008 86 #define DMA_IPL(x) (((x) - 3) << 4) 87 #define DMA_LWORD 0x0100 88 #define DMA_START 0x8000 89 90 /* status bits */ 91 #define DMA_ARMED 0x01 92 #define DMA_INTR 0x02 93 #define DMA_ACC 0x04 94 #define DMA_HALT 0x08 95 #define DMA_BERR 0x10 96 #define DMA_ALIGN 0x20 97 #define DMA_WRAP 0x40 98 99 #ifdef KERNEL 100 /* 101 * Macros to attempt to hide the HW differences between the 98620B DMA 102 * board and the 1TQ4-0401 DMA chip (68020C "board"). The latter 103 * includes emulation registers for the former but you need to access 104 * the "native-mode" registers directly in order to do 32-bit DMA. 105 * 106 * DMA_CLEAR: Clear interrupt on DMA board. We just use the 107 * emulation registers on the 98620C as that is easiest. 108 * DMA_STAT: Read status register. Again, we always read the 109 * emulation register. Someday we might want to 110 * look at the 98620C status to get the extended bits. 111 * DMA_ARM: Load address, count and kick-off DMA. 112 */ 113 #define DMA_CLEAR(dc) { v_int dmaclr = (int)dc->sc_Bhwaddr->dmaB_addr; } 114 #define DMA_STAT(dc) dc->sc_Bhwaddr->dmaB_stat 115 116 #if defined(HP320) 117 #define DMA_ARM(dc) \ 118 if (dc->sc_type == DMA_B) { \ 119 register struct dmaBdevice *dma = dc->sc_Bhwaddr; \ 120 dma->dmaB_addr = dc->sc_cur->dc_addr; \ 121 dma->dmaB_count = dc->sc_cur->dc_count - 1; \ 122 dma->dmaB_cmd = dc->sc_cmd; \ 123 } else { \ 124 register struct dmadevice *dma = dc->sc_hwaddr; \ 125 dma->dma_addr = dc->sc_cur->dc_addr; \ 126 dma->dma_count = dc->sc_cur->dc_count - 1; \ 127 dma->dma_cmd = dc->sc_cmd; \ 128 } 129 #else 130 #define DMA_ARM(dc) \ 131 { \ 132 register struct dmadevice *dma = dc->sc_hwaddr; \ 133 dma->dma_addr = dc->sc_cur->dc_addr; \ 134 dma->dma_count = dc->sc_cur->dc_count - 1; \ 135 dma->dma_cmd = dc->sc_cmd; \ 136 } 137 #endif 138 #endif 139