1 /* 2 * Copyright (c) 1982, 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)dma.c 7.5 (Berkeley) 5/4/91 34 * $Id: dma.c,v 1.2 1993/08/01 19:24:02 mycroft Exp $ 35 */ 36 37 /* 38 * DMA driver 39 */ 40 41 #include "param.h" 42 #include "systm.h" 43 #include "time.h" 44 #include "kernel.h" 45 #include "proc.h" 46 47 #include "dmareg.h" 48 #include "dmavar.h" 49 #include "device.h" 50 51 #include "../include/cpu.h" 52 #include "../hp300/isr.h" 53 54 extern void isrlink(); 55 extern void _insque(); 56 extern void _remque(); 57 extern void timeout(); 58 extern u_int kvtop(); 59 extern void PCIA(); 60 61 /* 62 * The largest single request will be MAXPHYS bytes which will require 63 * at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of 64 * the buffer pages are physically contiguous (MAXPHYS/NBPG) and the 65 * buffer is not page aligned (+1). 66 */ 67 #define DMAMAXIO (MAXPHYS/NBPG+1) 68 69 struct dma_chain { 70 int dc_count; 71 char *dc_addr; 72 }; 73 74 struct dma_softc { 75 struct dmadevice *sc_hwaddr; 76 struct dmaBdevice *sc_Bhwaddr; 77 char sc_type; 78 char sc_flags; 79 u_short sc_cmd; 80 struct dma_chain *sc_cur; 81 struct dma_chain *sc_last; 82 struct dma_chain sc_chain[DMAMAXIO]; 83 } dma_softc[NDMA]; 84 85 /* types */ 86 #define DMA_B 0 87 #define DMA_C 1 88 89 /* flags */ 90 #define DMAF_PCFLUSH 0x01 91 #define DMAF_VCFLUSH 0x02 92 #define DMAF_NOINTR 0x04 93 94 struct devqueue dmachan[NDMA + 1]; 95 int dmaintr(); 96 97 #ifdef DEBUG 98 int dmadebug = 0; 99 #define DDB_WORD 0x01 /* same as DMAGO_WORD */ 100 #define DDB_LWORD 0x02 /* same as DMAGO_LWORD */ 101 #define DDB_FOLLOW 0x04 102 #define DDB_IO 0x08 103 104 void dmatimeout(); 105 int dmatimo[NDMA]; 106 107 long dmahits[NDMA]; 108 long dmamisses[NDMA]; 109 long dmabyte[NDMA]; 110 long dmaword[NDMA]; 111 long dmalword[NDMA]; 112 #endif 113 114 void 115 dmainit() 116 { 117 register struct dmareg *dma = (struct dmareg *)DMA_BASE; 118 register struct dma_softc *dc; 119 register int i; 120 char rev; 121 122 /* 123 * Determine the DMA type. 124 * Don't know how to easily differentiate the A and B cards, 125 * so we just hope nobody has an A card (A cards will work if 126 * DMAINTLVL is set to 3). 127 */ 128 if (!badbaddr((char *)&dma->dma_id[2])) 129 rev = dma->dma_id[2]; 130 else { 131 rev = 'B'; 132 #if !defined(HP320) 133 panic("dmainit: DMA card requires hp320 support"); 134 #endif 135 } 136 137 dc = &dma_softc[0]; 138 for (i = 0; i < NDMA; i++) { 139 dc->sc_hwaddr = (i & 1) ? &dma->dma_chan1 : &dma->dma_chan0; 140 dc->sc_Bhwaddr = (i & 1) ? &dma->dma_Bchan1 : &dma->dma_Bchan0; 141 dc->sc_type = rev == 'B' ? DMA_B : DMA_C; 142 dc++; 143 dmachan[i].dq_forw = dmachan[i].dq_back = &dmachan[i]; 144 } 145 dmachan[i].dq_forw = dmachan[i].dq_back = &dmachan[i]; 146 #ifdef DEBUG 147 /* make sure timeout is really not needed */ 148 timeout(dmatimeout, 0, 30 * hz); 149 #endif 150 151 printf("dma: 98620%c with 2 channels, %d bit DMA\n", 152 rev, rev == 'B' ? 16 : 32); 153 } 154 155 int 156 dmareq(dq) 157 register struct devqueue *dq; 158 { 159 register int i; 160 register int chan; 161 register int s = splbio(); 162 163 chan = dq->dq_ctlr; 164 i = NDMA; 165 while (--i >= 0) { 166 if ((chan & (1 << i)) == 0) 167 continue; 168 if (dmachan[i].dq_forw != &dmachan[i]) 169 continue; 170 insque(dq, &dmachan[i]); 171 dq->dq_ctlr = i; 172 splx(s); 173 return(1); 174 } 175 insque(dq, dmachan[NDMA].dq_back); 176 splx(s); 177 return(0); 178 } 179 180 void 181 dmafree(dq) 182 register struct devqueue *dq; 183 { 184 int unit = dq->dq_ctlr; 185 register struct dma_softc *dc = &dma_softc[unit]; 186 register struct devqueue *dn; 187 register int chan, s; 188 189 s = splbio(); 190 #ifdef DEBUG 191 dmatimo[unit] = 0; 192 #endif 193 DMA_CLEAR(dc); 194 /* 195 * XXX we may not always go thru the flush code in dmastop() 196 */ 197 #if defined(HP360) || defined(HP370) 198 if (dc->sc_flags & DMAF_PCFLUSH) { 199 PCIA(); 200 dc->sc_flags &= ~DMAF_PCFLUSH; 201 } 202 #endif 203 #if defined(HP320) || defined(HP350) 204 if (dc->sc_flags & DMAF_VCFLUSH) { 205 /* 206 * 320/350s have VACs that may also need flushing. 207 * In our case we only flush the supervisor side 208 * because we know that if we are DMAing to user 209 * space, the physical pages will also be mapped 210 * in kernel space (via vmapbuf) and hence cache- 211 * inhibited by the pmap module due to the multiple 212 * mapping. 213 */ 214 DCIS(); 215 dc->sc_flags &= ~DMAF_VCFLUSH; 216 } 217 #endif 218 remque(dq); 219 chan = 1 << unit; 220 for (dn = dmachan[NDMA].dq_forw; 221 dn != &dmachan[NDMA]; dn = dn->dq_forw) { 222 if (dn->dq_ctlr & chan) { 223 remque((caddr_t)dn); 224 insque((caddr_t)dn, (caddr_t)dq->dq_back); 225 splx(s); 226 dn->dq_ctlr = dq->dq_ctlr; 227 (dn->dq_driver->d_start)(dn->dq_unit); 228 return; 229 } 230 } 231 splx(s); 232 } 233 234 void 235 dmago(unit, addr, count, flags) 236 int unit; 237 register char *addr; 238 register int count; 239 register int flags; 240 { 241 register struct dma_softc *dc = &dma_softc[unit]; 242 register struct dma_chain *dcp; 243 register char *dmaend = NULL; 244 register int tcount; 245 246 if (count > MAXPHYS) 247 panic("dmago: count > MAXPHYS"); 248 #if defined(HP320) 249 if (dc->sc_type == DMA_B && (flags & DMAGO_LWORD)) 250 panic("dmago: no can do 32-bit DMA"); 251 #endif 252 #ifdef DEBUG 253 if (dmadebug & DDB_FOLLOW) 254 printf("dmago(%d, %x, %x, %x)\n", 255 unit, addr, count, flags); 256 if (flags & DMAGO_LWORD) 257 dmalword[unit]++; 258 else if (flags & DMAGO_WORD) 259 dmaword[unit]++; 260 else 261 dmabyte[unit]++; 262 #endif 263 /* 264 * Build the DMA chain 265 */ 266 for (dcp = dc->sc_chain; count > 0; dcp++) { 267 dcp->dc_addr = (char *) kvtop(addr); 268 if (count < (tcount = NBPG - ((int)addr & PGOFSET))) 269 tcount = count; 270 dcp->dc_count = tcount; 271 addr += tcount; 272 count -= tcount; 273 if (flags & DMAGO_LWORD) 274 tcount >>= 2; 275 else if (flags & DMAGO_WORD) 276 tcount >>= 1; 277 if (dcp->dc_addr == dmaend 278 #if defined(HP320) 279 /* only 16-bit count on 98620B */ 280 && (dc->sc_type != DMA_B || 281 (dcp-1)->dc_count + tcount <= 65536) 282 #endif 283 ) { 284 #ifdef DEBUG 285 dmahits[unit]++; 286 #endif 287 dmaend += dcp->dc_count; 288 (--dcp)->dc_count += tcount; 289 } else { 290 #ifdef DEBUG 291 dmamisses[unit]++; 292 #endif 293 dmaend = dcp->dc_addr + dcp->dc_count; 294 dcp->dc_count = tcount; 295 } 296 } 297 dc->sc_cur = dc->sc_chain; 298 dc->sc_last = --dcp; 299 dc->sc_flags = 0; 300 /* 301 * Set up the command word based on flags 302 */ 303 dc->sc_cmd = DMA_ENAB | DMA_IPL(DMAINTLVL) | DMA_START; 304 if ((flags & DMAGO_READ) == 0) 305 dc->sc_cmd |= DMA_WRT; 306 if (flags & DMAGO_LWORD) 307 dc->sc_cmd |= DMA_LWORD; 308 else if (flags & DMAGO_WORD) 309 dc->sc_cmd |= DMA_WORD; 310 if (flags & DMAGO_PRI) 311 dc->sc_cmd |= DMA_PRI; 312 #if defined(HP360) || defined(HP370) 313 /* 314 * Remember if we need to flush external physical cache when 315 * DMA is done. We only do this if we are reading (writing memory). 316 */ 317 if (ectype == EC_PHYS && (flags & DMAGO_READ)) 318 dc->sc_flags |= DMAF_PCFLUSH; 319 #endif 320 #if defined(HP320) || defined(HP350) 321 if (ectype == EC_VIRT && (flags & DMAGO_READ)) 322 dc->sc_flags |= DMAF_VCFLUSH; 323 #endif 324 /* 325 * Remember if we can skip the dma completion interrupt on 326 * the last segment in the chain. 327 */ 328 if (flags & DMAGO_NOINT) { 329 if (dc->sc_cur == dc->sc_last) 330 dc->sc_cmd &= ~DMA_ENAB; 331 else 332 dc->sc_flags |= DMAF_NOINTR; 333 } 334 #ifdef DEBUG 335 if (dmadebug & DDB_IO) 336 if ((dmadebug&DDB_WORD) && (dc->sc_cmd&DMA_WORD) || 337 (dmadebug&DDB_LWORD) && (dc->sc_cmd&DMA_LWORD)) { 338 printf("dmago: cmd %x, flags %x\n", 339 dc->sc_cmd, dc->sc_flags); 340 for (dcp = dc->sc_chain; dcp <= dc->sc_last; dcp++) 341 printf(" %d: %d@%x\n", dcp-dc->sc_chain, 342 dcp->dc_count, dcp->dc_addr); 343 } 344 dmatimo[unit] = 1; 345 #endif 346 DMA_ARM(dc); 347 } 348 349 void 350 dmastop(unit) 351 register int unit; 352 { 353 register struct dma_softc *dc = &dma_softc[unit]; 354 register struct devqueue *dq; 355 356 #ifdef DEBUG 357 if (dmadebug & DDB_FOLLOW) 358 printf("dmastop(%d)\n", unit); 359 dmatimo[unit] = 0; 360 #endif 361 DMA_CLEAR(dc); 362 #if defined(HP360) || defined(HP370) 363 if (dc->sc_flags & DMAF_PCFLUSH) { 364 PCIA(); 365 dc->sc_flags &= ~DMAF_PCFLUSH; 366 } 367 #endif 368 #if defined(HP320) || defined(HP350) 369 if (dc->sc_flags & DMAF_VCFLUSH) { 370 /* 371 * 320/350s have VACs that may also need flushing. 372 * In our case we only flush the supervisor side 373 * because we know that if we are DMAing to user 374 * space, the physical pages will also be mapped 375 * in kernel space (via vmapbuf) and hence cache- 376 * inhibited by the pmap module due to the multiple 377 * mapping. 378 */ 379 DCIS(); 380 dc->sc_flags &= ~DMAF_VCFLUSH; 381 } 382 #endif 383 /* 384 * We may get this interrupt after a device service routine 385 * has freed the dma channel. So, ignore the intr if there's 386 * nothing on the queue. 387 */ 388 dq = dmachan[unit].dq_forw; 389 if (dq != &dmachan[unit]) 390 (dq->dq_driver->d_done)(dq->dq_unit); 391 } 392 393 int 394 dmaintr() 395 { 396 register struct dma_softc *dc; 397 register int i, stat; 398 int found = 0; 399 400 #ifdef DEBUG 401 if (dmadebug & DDB_FOLLOW) 402 printf("dmaintr\n"); 403 #endif 404 for (i = 0, dc = dma_softc; i < NDMA; i++, dc++) { 405 stat = DMA_STAT(dc); 406 if ((stat & DMA_INTR) == 0) 407 continue; 408 found++; 409 #ifdef DEBUG 410 if (dmadebug & DDB_IO) { 411 if ((dmadebug&DDB_WORD) && (dc->sc_cmd&DMA_WORD) || 412 (dmadebug&DDB_LWORD) && (dc->sc_cmd&DMA_LWORD)) 413 printf("dmaintr: unit %d stat %x next %d\n", 414 i, stat, (dc->sc_cur-dc->sc_chain)+1); 415 } 416 if (stat & DMA_ARMED) 417 printf("dma%d: intr when armed\n", i); 418 #endif 419 if (++dc->sc_cur <= dc->sc_last) { 420 #ifdef DEBUG 421 dmatimo[i] = 1; 422 #endif 423 /* 424 * Last chain segment, disable DMA interrupt. 425 */ 426 if (dc->sc_cur == dc->sc_last && 427 (dc->sc_flags & DMAF_NOINTR)) 428 dc->sc_cmd &= ~DMA_ENAB; 429 DMA_CLEAR(dc); 430 DMA_ARM(dc); 431 } else 432 dmastop(i); 433 } 434 return(found); 435 } 436 437 #ifdef DEBUG 438 void 439 dmatimeout() 440 { 441 register int i, s; 442 443 for (i = 0; i < NDMA; i++) { 444 s = splbio(); 445 if (dmatimo[i]) { 446 if (dmatimo[i] > 1) 447 printf("dma%d: timeout #%d\n", 448 i, dmatimo[i]-1); 449 dmatimo[i]++; 450 } 451 splx(s); 452 } 453 timeout(dmatimeout, (caddr_t)0, 30 * hz); 454 } 455 #endif 456