1 /* $NetBSD: dma.c,v 1.25 2000/03/23 06:37:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1982, 1990, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)dma.c 8.1 (Berkeley) 6/10/93 72 */ 73 74 /* 75 * DMA driver 76 */ 77 78 #include <machine/hp300spu.h> /* XXX param.h includes cpu.h */ 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/proc.h> 86 #include <sys/device.h> 87 88 #include <machine/frame.h> 89 #include <machine/cpu.h> 90 #include <machine/intr.h> 91 92 #include <hp300/dev/dmareg.h> 93 #include <hp300/dev/dmavar.h> 94 95 /* 96 * The largest single request will be MAXPHYS bytes which will require 97 * at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of 98 * the buffer pages are physically contiguous (MAXPHYS/NBPG) and the 99 * buffer is not page aligned (+1). 100 */ 101 #define DMAMAXIO (MAXPHYS/NBPG+1) 102 103 struct dma_chain { 104 int dc_count; 105 char *dc_addr; 106 }; 107 108 struct dma_channel { 109 struct dmaqueue *dm_job; /* current job */ 110 struct dmadevice *dm_hwaddr; /* registers if DMA_C */ 111 struct dmaBdevice *dm_Bhwaddr; /* registers if not DMA_C */ 112 char dm_flags; /* misc. flags */ 113 u_short dm_cmd; /* DMA controller command */ 114 int dm_cur; /* current segment */ 115 int dm_last; /* last segment */ 116 struct dma_chain dm_chain[DMAMAXIO]; /* all segments */ 117 }; 118 119 struct dma_softc { 120 struct dmareg *sc_dmareg; /* pointer to our hardware */ 121 struct dma_channel sc_chan[NDMACHAN]; /* 2 channels */ 122 TAILQ_HEAD(, dmaqueue) sc_queue; /* job queue */ 123 struct callout sc_debug_ch; 124 char sc_type; /* A, B, or C */ 125 int sc_ipl; /* our interrupt level */ 126 void *sc_ih; /* interrupt cookie */ 127 } dma_softc; 128 129 /* types */ 130 #define DMA_B 0 131 #define DMA_C 1 132 133 /* flags */ 134 #define DMAF_PCFLUSH 0x01 135 #define DMAF_VCFLUSH 0x02 136 #define DMAF_NOINTR 0x04 137 138 int dmaintr __P((void *)); 139 140 #ifdef DEBUG 141 int dmadebug = 0; 142 #define DDB_WORD 0x01 /* same as DMAGO_WORD */ 143 #define DDB_LWORD 0x02 /* same as DMAGO_LWORD */ 144 #define DDB_FOLLOW 0x04 145 #define DDB_IO 0x08 146 147 void dmatimeout __P((void *)); 148 int dmatimo[NDMACHAN]; 149 150 long dmahits[NDMACHAN]; 151 long dmamisses[NDMACHAN]; 152 long dmabyte[NDMACHAN]; 153 long dmaword[NDMACHAN]; 154 long dmalword[NDMACHAN]; 155 #endif 156 157 /* 158 * Initialize the DMA engine, called by dioattach() 159 */ 160 void 161 dmainit() 162 { 163 struct dma_softc *sc = &dma_softc; 164 struct dmareg *dma; 165 struct dma_channel *dc; 166 int i; 167 char rev; 168 169 /* There's just one. */ 170 sc->sc_dmareg = (struct dmareg *)DMA_BASE; 171 dma = sc->sc_dmareg; 172 173 /* 174 * Determine the DMA type. A DMA_A or DMA_B will fail the 175 * following probe. 176 * 177 * XXX Don't know how to easily differentiate the A and B cards, 178 * so we just hope nobody has an A card (A cards will work if 179 * splbio works out to ipl 3). 180 */ 181 if (badbaddr((char *)&dma->dma_id[2])) { 182 rev = 'B'; 183 #if !defined(HP320) 184 panic("dmainit: DMA card requires hp320 support"); 185 #endif 186 } else 187 rev = dma->dma_id[2]; 188 189 sc->sc_type = (rev == 'B') ? DMA_B : DMA_C; 190 191 TAILQ_INIT(&sc->sc_queue); 192 callout_init(&sc->sc_debug_ch); 193 194 for (i = 0; i < NDMACHAN; i++) { 195 dc = &sc->sc_chan[i]; 196 dc->dm_job = NULL; 197 switch (i) { 198 case 0: 199 dc->dm_hwaddr = &dma->dma_chan0; 200 dc->dm_Bhwaddr = &dma->dma_Bchan0; 201 break; 202 203 case 1: 204 dc->dm_hwaddr = &dma->dma_chan1; 205 dc->dm_Bhwaddr = &dma->dma_Bchan1; 206 break; 207 208 default: 209 panic("dmainit: more than 2 channels?"); 210 /* NOTREACHED */ 211 } 212 } 213 214 #ifdef DEBUG 215 /* make sure timeout is really not needed */ 216 callout_reset(&sc->sc_debug_ch, 30 * hz, dmatimeout, sc); 217 #endif 218 219 printf("98620%c, 2 channels, %d bit DMA\n", 220 rev, (rev == 'B') ? 16 : 32); 221 222 /* 223 * Defer hooking up our interrupt until the first 224 * DMA-using controller has hooked up theirs. 225 */ 226 sc->sc_ih = NULL; 227 } 228 229 /* 230 * Compute the ipl and (re)establish the interrupt handler 231 * for the DMA controller. 232 */ 233 void 234 dmacomputeipl() 235 { 236 struct dma_softc *sc = &dma_softc; 237 238 if (sc->sc_ih != NULL) 239 intr_disestablish(sc->sc_ih); 240 241 /* 242 * Our interrupt level must be as high as the highest 243 * device using DMA (i.e. splbio). 244 */ 245 sc->sc_ipl = PSLTOIPL(hp300_ipls[HP300_IPL_BIO]); 246 sc->sc_ih = intr_establish(dmaintr, sc, sc->sc_ipl, IPL_BIO); 247 } 248 249 int 250 dmareq(dq) 251 struct dmaqueue *dq; 252 { 253 struct dma_softc *sc = &dma_softc; 254 int i, chan, s; 255 256 #if 1 257 s = splhigh(); /* XXXthorpej */ 258 #else 259 s = splbio(); 260 #endif 261 262 chan = dq->dq_chan; 263 for (i = NDMACHAN - 1; i >= 0; i--) { 264 /* 265 * Can we use this channel? 266 */ 267 if ((chan & (1 << i)) == 0) 268 continue; 269 270 /* 271 * We can use it; is it busy? 272 */ 273 if (sc->sc_chan[i].dm_job != NULL) 274 continue; 275 276 /* 277 * Not busy; give the caller this channel. 278 */ 279 sc->sc_chan[i].dm_job = dq; 280 dq->dq_chan = i; 281 splx(s); 282 return (1); 283 } 284 285 /* 286 * Couldn't get a channel now; put this in the queue. 287 */ 288 TAILQ_INSERT_TAIL(&sc->sc_queue, dq, dq_list); 289 splx(s); 290 return (0); 291 } 292 293 void 294 dmafree(dq) 295 struct dmaqueue *dq; 296 { 297 int unit = dq->dq_chan; 298 struct dma_softc *sc = &dma_softc; 299 struct dma_channel *dc = &sc->sc_chan[unit]; 300 struct dmaqueue *dn; 301 int chan, s; 302 303 #if 1 304 s = splhigh(); /* XXXthorpej */ 305 #else 306 s = splbio(); 307 #endif 308 309 #ifdef DEBUG 310 dmatimo[unit] = 0; 311 #endif 312 313 DMA_CLEAR(dc); 314 315 #if defined(CACHE_HAVE_PAC) || defined(M68040) 316 /* 317 * XXX we may not always go thru the flush code in dmastop() 318 */ 319 if (dc->dm_flags & DMAF_PCFLUSH) { 320 PCIA(); 321 dc->dm_flags &= ~DMAF_PCFLUSH; 322 } 323 #endif 324 325 #if defined(CACHE_HAVE_VAC) 326 if (dc->dm_flags & DMAF_VCFLUSH) { 327 /* 328 * 320/350s have VACs that may also need flushing. 329 * In our case we only flush the supervisor side 330 * because we know that if we are DMAing to user 331 * space, the physical pages will also be mapped 332 * in kernel space (via vmapbuf) and hence cache- 333 * inhibited by the pmap module due to the multiple 334 * mapping. 335 */ 336 DCIS(); 337 dc->dm_flags &= ~DMAF_VCFLUSH; 338 } 339 #endif 340 341 /* 342 * Channel is now free. Look for another job to run on this 343 * channel. 344 */ 345 dc->dm_job = NULL; 346 chan = 1 << unit; 347 for (dn = sc->sc_queue.tqh_first; dn != NULL; 348 dn = dn->dq_list.tqe_next) { 349 if (dn->dq_chan & chan) { 350 /* Found one... */ 351 TAILQ_REMOVE(&sc->sc_queue, dn, dq_list); 352 dc->dm_job = dn; 353 dn->dq_chan = dq->dq_chan; 354 splx(s); 355 356 /* Start the initiator. */ 357 (*dn->dq_start)(dn->dq_softc); 358 return; 359 } 360 } 361 splx(s); 362 } 363 364 void 365 dmago(unit, addr, count, flags) 366 int unit; 367 char *addr; 368 int count; 369 int flags; 370 { 371 struct dma_softc *sc = &dma_softc; 372 struct dma_channel *dc = &sc->sc_chan[unit]; 373 char *dmaend = NULL; 374 int seg, tcount; 375 376 if (count > MAXPHYS) 377 panic("dmago: count > MAXPHYS"); 378 379 #if defined(HP320) 380 if (sc->sc_type == DMA_B && (flags & DMAGO_LWORD)) 381 panic("dmago: no can do 32-bit DMA"); 382 #endif 383 384 #ifdef DEBUG 385 if (dmadebug & DDB_FOLLOW) 386 printf("dmago(%d, %p, %x, %x)\n", 387 unit, addr, count, flags); 388 if (flags & DMAGO_LWORD) 389 dmalword[unit]++; 390 else if (flags & DMAGO_WORD) 391 dmaword[unit]++; 392 else 393 dmabyte[unit]++; 394 #endif 395 /* 396 * Build the DMA chain 397 */ 398 for (seg = 0; count > 0; seg++) { 399 dc->dm_chain[seg].dc_addr = (char *) kvtop(addr); 400 #if defined(M68040) 401 /* 402 * Push back dirty cache lines 403 */ 404 if (mmutype == MMU_68040) 405 DCFP((paddr_t)dc->dm_chain[seg].dc_addr); 406 #endif 407 if (count < (tcount = NBPG - ((int)addr & PGOFSET))) 408 tcount = count; 409 dc->dm_chain[seg].dc_count = tcount; 410 addr += tcount; 411 count -= tcount; 412 if (flags & DMAGO_LWORD) 413 tcount >>= 2; 414 else if (flags & DMAGO_WORD) 415 tcount >>= 1; 416 417 /* 418 * Try to compact the DMA transfer if the pages are adjacent. 419 * Note: this will never happen on the first iteration. 420 */ 421 if (dc->dm_chain[seg].dc_addr == dmaend 422 #if defined(HP320) 423 /* only 16-bit count on 98620B */ 424 && (sc->sc_type != DMA_B || 425 dc->dm_chain[seg - 1].dc_count + tcount <= 65536) 426 #endif 427 ) { 428 #ifdef DEBUG 429 dmahits[unit]++; 430 #endif 431 dmaend += dc->dm_chain[seg].dc_count; 432 dc->dm_chain[--seg].dc_count += tcount; 433 } else { 434 #ifdef DEBUG 435 dmamisses[unit]++; 436 #endif 437 dmaend = dc->dm_chain[seg].dc_addr + 438 dc->dm_chain[seg].dc_count; 439 dc->dm_chain[seg].dc_count = tcount; 440 } 441 } 442 dc->dm_cur = 0; 443 dc->dm_last = --seg; 444 dc->dm_flags = 0; 445 /* 446 * Set up the command word based on flags 447 */ 448 dc->dm_cmd = DMA_ENAB | DMA_IPL(sc->sc_ipl) | DMA_START; 449 if ((flags & DMAGO_READ) == 0) 450 dc->dm_cmd |= DMA_WRT; 451 if (flags & DMAGO_LWORD) 452 dc->dm_cmd |= DMA_LWORD; 453 else if (flags & DMAGO_WORD) 454 dc->dm_cmd |= DMA_WORD; 455 if (flags & DMAGO_PRI) 456 dc->dm_cmd |= DMA_PRI; 457 458 #if defined(M68040) 459 /* 460 * On the 68040 we need to flush (push) the data cache before a 461 * DMA (already done above) and flush again after DMA completes. 462 * In theory we should only need to flush prior to a write DMA 463 * and purge after a read DMA but if the entire page is not 464 * involved in the DMA we might purge some valid data. 465 */ 466 if (mmutype == MMU_68040 && (flags & DMAGO_READ)) 467 dc->dm_flags |= DMAF_PCFLUSH; 468 #endif 469 470 #if defined(CACHE_HAVE_PAC) 471 /* 472 * Remember if we need to flush external physical cache when 473 * DMA is done. We only do this if we are reading (writing memory). 474 */ 475 if (ectype == EC_PHYS && (flags & DMAGO_READ)) 476 dc->dm_flags |= DMAF_PCFLUSH; 477 #endif 478 479 #if defined(CACHE_HAVE_VAC) 480 if (ectype == EC_VIRT && (flags & DMAGO_READ)) 481 dc->dm_flags |= DMAF_VCFLUSH; 482 #endif 483 484 /* 485 * Remember if we can skip the dma completion interrupt on 486 * the last segment in the chain. 487 */ 488 if (flags & DMAGO_NOINT) { 489 if (dc->dm_cur == dc->dm_last) 490 dc->dm_cmd &= ~DMA_ENAB; 491 else 492 dc->dm_flags |= DMAF_NOINTR; 493 } 494 #ifdef DEBUG 495 if (dmadebug & DDB_IO) { 496 if (((dmadebug&DDB_WORD) && (dc->dm_cmd&DMA_WORD)) || 497 ((dmadebug&DDB_LWORD) && (dc->dm_cmd&DMA_LWORD))) { 498 printf("dmago: cmd %x, flags %x\n", 499 dc->dm_cmd, dc->dm_flags); 500 for (seg = 0; seg <= dc->dm_last; seg++) 501 printf(" %d: %d@%p\n", seg, 502 dc->dm_chain[seg].dc_count, 503 dc->dm_chain[seg].dc_addr); 504 } 505 } 506 dmatimo[unit] = 1; 507 #endif 508 DMA_ARM(sc, dc); 509 } 510 511 void 512 dmastop(unit) 513 int unit; 514 { 515 struct dma_softc *sc = &dma_softc; 516 struct dma_channel *dc = &sc->sc_chan[unit]; 517 518 #ifdef DEBUG 519 if (dmadebug & DDB_FOLLOW) 520 printf("dmastop(%d)\n", unit); 521 dmatimo[unit] = 0; 522 #endif 523 DMA_CLEAR(dc); 524 525 #if defined(CACHE_HAVE_PAC) || defined(M68040) 526 if (dc->dm_flags & DMAF_PCFLUSH) { 527 PCIA(); 528 dc->dm_flags &= ~DMAF_PCFLUSH; 529 } 530 #endif 531 532 #if defined(CACHE_HAVE_VAC) 533 if (dc->dm_flags & DMAF_VCFLUSH) { 534 /* 535 * 320/350s have VACs that may also need flushing. 536 * In our case we only flush the supervisor side 537 * because we know that if we are DMAing to user 538 * space, the physical pages will also be mapped 539 * in kernel space (via vmapbuf) and hence cache- 540 * inhibited by the pmap module due to the multiple 541 * mapping. 542 */ 543 DCIS(); 544 dc->dm_flags &= ~DMAF_VCFLUSH; 545 } 546 #endif 547 548 /* 549 * We may get this interrupt after a device service routine 550 * has freed the dma channel. So, ignore the intr if there's 551 * nothing on the queue. 552 */ 553 if (dc->dm_job != NULL) 554 (*dc->dm_job->dq_done)(dc->dm_job->dq_softc); 555 } 556 557 int 558 dmaintr(arg) 559 void *arg; 560 { 561 struct dma_softc *sc = arg; 562 struct dma_channel *dc; 563 int i, stat; 564 int found = 0; 565 566 #ifdef DEBUG 567 if (dmadebug & DDB_FOLLOW) 568 printf("dmaintr\n"); 569 #endif 570 for (i = 0; i < NDMACHAN; i++) { 571 dc = &sc->sc_chan[i]; 572 stat = DMA_STAT(dc); 573 if ((stat & DMA_INTR) == 0) 574 continue; 575 found++; 576 #ifdef DEBUG 577 if (dmadebug & DDB_IO) { 578 if (((dmadebug&DDB_WORD) && (dc->dm_cmd&DMA_WORD)) || 579 ((dmadebug&DDB_LWORD) && (dc->dm_cmd&DMA_LWORD))) 580 printf("dmaintr: flags %x unit %d stat %x next %d\n", 581 dc->dm_flags, i, stat, dc->dm_cur + 1); 582 } 583 if (stat & DMA_ARMED) 584 printf("dma channel %d: intr when armed\n", i); 585 #endif 586 /* 587 * Load the next segemnt, or finish up if we're done. 588 */ 589 dc->dm_cur++; 590 if (dc->dm_cur <= dc->dm_last) { 591 #ifdef DEBUG 592 dmatimo[i] = 1; 593 #endif 594 /* 595 * If we're the last segment, disable the 596 * completion interrupt, if necessary. 597 */ 598 if (dc->dm_cur == dc->dm_last && 599 (dc->dm_flags & DMAF_NOINTR)) 600 dc->dm_cmd &= ~DMA_ENAB; 601 DMA_CLEAR(dc); 602 DMA_ARM(sc, dc); 603 } else 604 dmastop(i); 605 } 606 return(found); 607 } 608 609 #ifdef DEBUG 610 void 611 dmatimeout(arg) 612 void *arg; 613 { 614 int i, s; 615 struct dma_softc *sc = arg; 616 617 for (i = 0; i < NDMACHAN; i++) { 618 s = splbio(); 619 if (dmatimo[i]) { 620 if (dmatimo[i] > 1) 621 printf("dma channel %d timeout #%d\n", 622 i, dmatimo[i]-1); 623 dmatimo[i]++; 624 } 625 splx(s); 626 } 627 callout_reset(&sc->sc_debug_ch, 30 * hz, dmatimeout, sc); 628 } 629 #endif 630