1 /* $NetBSD: zs_sbdio.c,v 1.12 2015/06/23 21:00:23 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: zs_sbdio.c,v 1.12 2015/06/23 21:00:23 matt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/tty.h> 46 #include <sys/conf.h> 47 #include <sys/intr.h> 48 49 #include <dev/cons.h> 50 #include <dev/ic/z8530reg.h> 51 52 #include <mips/locore.h> 53 54 #include <machine/sbdiovar.h> 55 #include <machine/z8530var.h> 56 57 #define ZS_DEFSPEED 9600 58 #define PCLK (9600 * 512) /* 4.915200MHz */ 59 60 /* The layout of this is hardware-dependent (padding, order). */ 61 struct zschan { 62 volatile uint8_t zc_csr; /* ctrl, status, and indirect access */ 63 uint8_t padding1[3]; 64 volatile uint8_t zc_data; /* data */ 65 uint8_t padding2[3]; 66 } __attribute__((__packed__)); 67 68 struct zsdevice { 69 /* Yes, they are backwards. */ 70 struct zschan zs_chan_b; 71 struct zschan zs_chan_a; 72 } __attribute__((__packed__)); 73 74 static uint8_t zs_init_reg[16] = { 75 0, /* 0: CMD (reset, etc.) */ 76 0, /* 1: No interrupts yet. */ 77 0, /* 2: IVECT EWS-UX don't set this. */ 78 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 79 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 80 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 81 0, /* 6: TXSYNC/SYNCLO */ 82 0, /* 7: RXSYNC/SYNCHI */ 83 0, /* 8: alias for data port */ 84 ZSWR9_MASTER_IE, 85 0, /* 10: Misc. TX/RX control bits */ 86 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 87 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /* 12: BAUDLO (default=9600) */ 88 0, /*13: BAUDHI (default=9600) */ 89 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 90 ZSWR15_BREAK_IE, 91 }; 92 93 static int zs_sbdio_match(device_t, cfdata_t, void *); 94 static void zs_sbdio_attach(device_t, device_t, void *); 95 96 CFATTACH_DECL_NEW(zsc_sbdio, sizeof(struct zsc_softc), 97 zs_sbdio_match, zs_sbdio_attach, NULL, NULL); 98 99 int 100 zs_sbdio_match(device_t parent, cfdata_t cf, void *aux) 101 { 102 struct sbdio_attach_args *sa = aux; 103 104 return strcmp(sa->sa_name, "zsc") ? 0 : 1; 105 } 106 107 void 108 zs_sbdio_attach(device_t parent, device_t self, void *aux) 109 { 110 struct zsc_softc *zsc = device_private(self); 111 struct sbdio_attach_args *sa = aux; 112 struct zsc_attach_args zsc_args; 113 struct zschan *zc; 114 struct zs_chanstate *cs; 115 struct zsdevice *zs_addr; 116 int s, channel; 117 118 zsc->zsc_dev = self; 119 aprint_normal("\n"); 120 121 zs_addr = (void *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1); 122 zsc->zsc_flags = sa->sa_flags; 123 124 /* 125 * Initialize software state for each channel. 126 */ 127 for (channel = 0; channel < 2; channel++) { 128 zsc_args.channel = channel; 129 zsc_args.hwflags = 0; 130 cs = &zsc->zsc_cs_store[channel]; 131 zsc->zsc_cs[channel] = cs; 132 133 cs->cs_channel = channel; 134 cs->cs_private = NULL; 135 cs->cs_ops = &zsops_null; 136 137 if (channel == 0) 138 zc = &zs_addr->zs_chan_a; 139 else 140 zc = &zs_addr->zs_chan_b; 141 142 if (zc == zs_consaddr) { 143 memcpy(cs, zs_conscs, sizeof(struct zs_chanstate)); 144 zs_conscs = cs; 145 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 146 } else { 147 cs->cs_reg_csr = &zc->zc_csr; 148 cs->cs_reg_data = &zc->zc_data; 149 memcpy(cs->cs_creg, zs_init_reg, 16); 150 memcpy(cs->cs_preg, zs_init_reg, 16); 151 cs->cs_defspeed = ZS_DEFSPEED; 152 zsc_args.hwflags = 0; 153 } 154 155 zs_lock_init(cs); 156 cs->cs_brg_clk = PCLK / 16; 157 cs->cs_defcflag = zs_def_cflag; 158 159 /* Make these correspond to cs_defcflag (-crtscts) */ 160 cs->cs_rr0_dcd = ZSRR0_DCD; 161 cs->cs_rr0_cts = 0; 162 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 163 cs->cs_wr5_rts = 0; 164 165 /* 166 * Clear the master interrupt enable. 167 * The INTENA is common to both channels, 168 * so just do it on the A channel. 169 */ 170 if (channel == 0) { 171 zs_write_reg(cs, 9, 0); 172 } 173 174 /* 175 * Look for a child driver for this channel. 176 * The child attach will setup the hardware. 177 */ 178 if (!config_found(self, (void *)&zsc_args, zs_print)) { 179 /* No sub-driver. Just reset it. */ 180 uint8_t reset = (channel == 0) ? 181 ZSWR9_A_RESET : ZSWR9_B_RESET; 182 s = splhigh(); 183 zs_write_reg(cs, 9, reset); 184 splx(s); 185 } 186 } 187 188 zsc->zsc_si = softint_establish(SOFTINT_SERIAL, 189 (void (*)(void *))zsc_intr_soft, zsc); 190 intr_establish(sa->sa_irq, zshard, zsc); 191 192 /* 193 * Set the master interrupt enable and interrupt vector. 194 * (common to both channels, do it on A) 195 */ 196 cs = zsc->zsc_cs[0]; 197 s = splhigh(); 198 /* interrupt vector */ 199 zs_write_reg(cs, 2, zs_init_reg[2]); 200 /* master interrupt control (enable) */ 201 zs_write_reg(cs, 9, zs_init_reg[9]); 202 splx(s); 203 } 204 205 /* 206 * console stuff 207 */ 208 209 static void zs_sbdio_cnprobe(struct consdev *); 210 static void zs_sbdio_cninit(struct consdev *); 211 212 struct consdev consdev_zs_sbdio = { 213 zs_sbdio_cnprobe, 214 zs_sbdio_cninit, 215 zscngetc, 216 zscnputc, 217 nullcnpollc, 218 NULL, 219 NULL, 220 NULL, 221 NODEV, 222 CN_DEAD 223 }; 224 225 static void 226 zs_sbdio_cnprobe(struct consdev *cn) 227 { 228 229 /* not used */ 230 } 231 232 static void 233 zs_sbdio_cninit(struct consdev *cn) 234 { 235 struct zs_chanstate *cs; 236 struct zschan *zc; 237 238 zc = zs_consaddr; 239 cs = zs_conscs; 240 241 /* Setup temporary chanstate. */ 242 cs->cs_reg_csr = &zc->zc_csr; 243 cs->cs_reg_data = &zc->zc_data; 244 245 /* Initialize the pending registers. */ 246 memcpy(cs->cs_preg, zs_init_reg, 16); 247 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 248 249 cs->cs_brg_clk = PCLK / 16; 250 cs->cs_defspeed = ZS_DEFSPEED; 251 zs_set_speed(cs, ZS_DEFSPEED); 252 253 /* Clear the master interrupt enable. */ 254 zs_write_reg(cs, 9, 0); 255 256 /* Reset the whole SCC chip. */ 257 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 258 259 /* Copy "pending" to "current" and H/W */ 260 zs_loadchannelregs(cs); 261 } 262