xref: /netbsd-src/sys/arch/ews4800mips/include/intr.h (revision aaf4ece63a859a04e37cf3a7229b5fab0157cc06)
1 /*	$NetBSD: intr.h,v 1.1 2005/12/29 15:20:08 tsutsui Exp $	*/
2 
3 /*-
4  * Copyright (c) 2000, 2001, 2004 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by the NetBSD
21  *	Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #ifndef _EWS4800MIPS_INTR_H_
40 #define	_EWS4800MIPS_INTR_H_
41 
42 #include <sys/device.h>
43 #include <sys/lock.h>
44 #include <sys/queue.h>
45 
46 #define IPL_NONE	0	/* disable only this interrupt */
47 
48 #define IPL_SOFT	1	/* generic software interrupts (SI 0) */
49 #define IPL_SOFTCLOCK	2	/* clock software interrupts (SI 0) */
50 #define IPL_SOFTNET	3	/* network software interrupts (SI 1) */
51 #define IPL_SOFTSERIAL	4	/* serial software interrupts (SI 1) */
52 
53 #define IPL_BIO		5	/* disable block I/O interrupts */
54 #define IPL_NET		6	/* disable network interrupts */
55 #define IPL_TTY		7	/* disable terminal interrupts */
56 #define IPL_SERIAL	7	/* disable serial interrupts */
57 #define IPL_CLOCK	8	/* disable clock interrupts */
58 #define IPL_HIGH	8	/* disable all interrupts */
59 
60 #define _IPL_NSOFT	4
61 #define _IPL_N		9
62 
63 #define _IPL_SI0_FIRST	IPL_SOFT
64 #define _IPL_SI0_LAST	IPL_SOFTCLOCK
65 
66 #define _IPL_SI1_FIRST	IPL_SOFTNET
67 #define _IPL_SI1_LAST	IPL_SOFTSERIAL
68 
69 #define IPL_SOFTNAMES {							\
70 	"misc",								\
71 	"clock",							\
72 	"net",								\
73 	"serial",							\
74 }
75 
76 #define IST_UNUSABLE	-1	/* interrupt cannot be used */
77 #define IST_NONE	0	/* none (dummy) */
78 #define IST_PULSE	1	/* pulsed */
79 #define IST_EDGE	2	/* edge-triggered */
80 #define IST_LEVEL	3	/* level-triggered */
81 
82 #ifdef _KERNEL
83 
84 extern const uint32_t *ipl_sr_bits;
85 extern const uint32_t ipl_si_to_sr[_IPL_NSOFT];
86 
87 extern int		_splraise(int);
88 extern int		_spllower(int);
89 extern int		_splset(int);
90 extern int		_splget(int);
91 extern int		_splnone(int);
92 extern int		_setsoftintr(int);
93 extern int		_clrsoftintr(int);
94 
95 #define splhigh()	_splraise(ipl_sr_bits[IPL_HIGH])
96 #define spl0()		(void) _spllower(0)
97 #define splx(s)		(void) _splset(s)
98 #define splbio()	_splraise(ipl_sr_bits[IPL_BIO])
99 #define splnet()	_splraise(ipl_sr_bits[IPL_NET])
100 #define spltty()	_splraise(ipl_sr_bits[IPL_TTY])
101 #define splserial()	_splraise(ipl_sr_bits[IPL_SERIAL])
102 #define splvm()		spltty()
103 #define splclock()	_splraise(ipl_sr_bits[IPL_CLOCK])
104 #define splstatclock()	splclock()
105 
106 #define splsched()	splclock()
107 #define spllock()	splhigh()
108 #define spllpt()	spltty()
109 
110 #define splsoft()	_splraise(ipl_sr_bits[IPL_SOFT])
111 #define splsoftclock()	_splraise(ipl_sr_bits[IPL_SOFTCLOCK])
112 #define splsoftnet()	_splraise(ipl_sr_bits[IPL_SOFTNET])
113 #define splsoftserial()	_splraise(ipl_sr_bits[IPL_SOFTSERIAL])
114 
115 #define spllowersoftclock() _spllower(ipl_sr_bits[IPL_SOFTCLOCK])
116 
117 void intr_init(void);
118 void intr_establish(int, int (*)(void *), void *);
119 void intr_disestablish(void *);
120 
121 #include <mips/softintr.h>
122 
123 #endif /* _KERNEL */
124 #endif /* !_EWS4800MIPS_INTR_H_ */
125