1 /* $NetBSD: intr.h,v 1.10 2008/04/28 20:23:18 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _EWS4800MIPS_INTR_H_ 33 #define _EWS4800MIPS_INTR_H_ 34 35 #define IPL_NONE 0 /* disable only this interrupt */ 36 #define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */ 37 #define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */ 38 #define IPL_SOFTNET 2 /* network software interrupts (SI 1) */ 39 #define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */ 40 #define IPL_VM 3 41 #define IPL_SCHED 4 /* disable clock interrupts */ 42 #define IPL_HIGH 4 /* disable all interrupts */ 43 44 #define _IPL_N 5 45 46 #define _IPL_SI0_FIRST IPL_SOFTCLOCK 47 #define _IPL_SI0_LAST IPL_SOFTBIO 48 49 #define _IPL_SI1_FIRST IPL_SOFTNET 50 #define _IPL_SI1_LAST IPL_SOFTSERIAL 51 52 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 53 #define IST_NONE 0 /* none (dummy) */ 54 #define IST_PULSE 1 /* pulsed */ 55 #define IST_EDGE 2 /* edge-triggered */ 56 #define IST_LEVEL 3 /* level-triggered */ 57 58 #include <mips/locore.h> 59 60 extern const uint32_t *ipl_sr_bits; 61 62 #define spl0() (void) _spllower(0) 63 #define splx(s) (void) _splset(s) 64 65 typedef int ipl_t; 66 typedef struct { 67 ipl_t _sr; 68 } ipl_cookie_t; 69 70 static inline ipl_cookie_t 71 makeiplcookie(ipl_t ipl) 72 { 73 74 return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]}; 75 } 76 77 static inline int 78 splraiseipl(ipl_cookie_t icookie) 79 { 80 81 return _splraise(icookie._sr); 82 } 83 84 #include <sys/spl.h> 85 86 void intr_init(void); 87 void intr_establish(int, int (*)(void *), void *); 88 void intr_disestablish(void *); 89 90 #endif /* !_EWS4800MIPS_INTR_H_ */ 91